Blog Review: Jan. 8

Cadence’s Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type.

Siemens EDA’s Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to debugging and coverage closure and notes some of the hurdles still to overcome.

Synopsys’ Stelios Diamantidis analyzes internal pilot projects that are deploying generative AI across sales, people, marketing, investor relations, and engineering teams, which have resulted in more than 1.5 million lines of software code developed using AI assistance and are expected to yield 250,000 hours of employee capacity in 2025.

Lam Research’s Wojtek Osowiecki, Martyn Coogans, Saravanapriyan Sriraman, Rakesh Ranjan, Joe Lu, and David M. Fried find that deploying virtual twins for hardware prototyping, process optimization, and device characterization significantly reduces the carbon footprint of semiconductor R&D compared to physical experimentation.

Arm’s Ola Liljedahl describes different user space delay and wait implementations for multithreaded applications on the Armv8+ architecture and recommends best practices for improving throughput and fair access to shared resources.

Keysight’s Chaimaa Aarab explores meeting the throughput requirements of 6G with a new frequency range that falls between sub-6 GHz and mmWave and the added complexities it brings for radio channel modeling.

Ansys’ Judy Curran argues for the use of simulation to design and validate the safety of new automotive features without expensive hardware testing, with applications ranging from materials and crash safety to smart lighting and ADAS functions.

SEMI’s Laith Altimime anticipates that integrated photonics will offer the semiconductor industry a new way to increase the speed and capability of classical compute functions and explores the current state of the ecosystem for III-V technologies.

Plus, catch up on the blogs featured in the latest Systems & Design newsletter:

Technology Editor Brian Bailey looks at which EDA stories got the most traffic over the past year and how they highlight the design and verification issues of 2024.

Cadence’s Sanjeet Kumar digs into a scalable I/O technology specifically designed for inside-the-box asymmetric USB applications.

Alphawave Semi’s Archana Cheruliyil shows why a custom implementation of HBM can be a performance differentiator that justifies its complexity.

Keysight’s Gabrielle Duncan examines the behaviors of materials and components under actual operating conditions.

Siemens’ Jeff Wilson zeroes in on how to deal with IR drop and electromigration early in the design process.

Arteris’ Andy Nightingale looks back on the year’s NoC advancements in modular scaling, cache coherence, and hardware/software integration.

Synopsys’ Vamsi Thatha focuses on the benefits of advanced parasitic extraction, power analysis, and physical checks in multi-die designs.