Blog Review: July 2

Synopsys’ Shankar Krishnamoorthy chats with industry experts about how the combination of AI and software-defined systems is driving a re-evaluation of engineering workflows and why chip, software, and system development must evolve in unison.

Siemens’ Jake Wiltgen considers the rapidly evolving and growing challenge of performing DFT verification as designs scale, with complex hierarchical DFT implementations that contain multiple DFT cores.

Cadence’s Tanushri Shah checks out how a hybrid control system for quantum computers eliminates friction between quantum and classical operations, enabling hybrid workflows to operate smoothly.

Arm’s Alex Spinelli considers the changing role of senior engineers and shows how technologists can transition effectively from traditional coding roles to becoming expert coaches and master debuggers for AI coding agents.

Ansys’ Marc Swinnen and Emily Gerken warn that mechanical and thermomechanical stresses during manufacturing and operation pose significant risks to the structural integrity of 3D-IC chip packages and use simulation to assess and optimize designs.

Keysight’s Heidi Garcia and Allison Freedman chat about the fundamental differences between AI/ML and traditional networks, why conventional Ethernet tuning falls short, and how to maximize the performance and efficiency of AI infrastructure.

In a blog for SEMI, Greene Tweed’s Carmen Quartapella explains the critical role of pendulum valves and their seals in semiconductor wafer processing and the specific risks faced by five major types of seals.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey opines that for many aspects of an EDA flow, hallucinations from AI are not really that serious because that is no worse than engineers on a Friday afternoon.

Keysight’s Nilesh Kamdar reflects on a panel discussion about the CHIPS Act’s impact on the design ecosystem, in Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation.

Cadence’s Moshiko Emmer talks about how ensuring trusted execution across multiple chiplets and vendors is more complex than in traditional monolithic SoCs.

Alphawave Semi’s Tony Chan Carusone explains how FPGAs can be used to identify bursts of errors in wireline networking and communications that otherwise would be missed.

Siemens’ Priyank Jain argues that debugging increasingly complex chips require a different approach.