Blog Review: July 3

Cadence’s Paul McLellan digs into 5G with a two-part post explaining the basics of the technology, what makes it so different from 4G, and the challenges ahead including the limitations of mmWave.

Synopsys’ Vikramjeet Bamel and Pankaj Sharma note the features that make GDDR6 a dominant memory in the high performance segment and allowing it to expand beyond graphics to automotive, AI, and AR/VR.

Mentor’s Brent Klingforth takes a look at how to speed up PCB design using advanced tools for placement and layout reuse.

Applied Materials’ Niranjan Khasgiwale argues that for new memories to reach high-volume manufacturing, the industry must enable new process control solutions capable of measuring pristine, as-deposited thin films quickly and non-invasively.

Arm’s Alessandro Grande chats with Joseph Dureau, CTO at Snips, about the role of voice interfaces, the need to move voice data processing to the device to protect user privacy, and creating open source releases within a business.

A Rambus writer considers the proliferation of counterfeit semiconductors, with one million counterfeit devices seized during a 2-week operation in 2017, and the risks posed to health and safety.

Silicon Labs’ Kevin Smith delves into advanced timing topics and the challenges of taking measurements to determine whether phase noise really is phase noise.

SEMI’s Serena Brischetto chats with Thomas Fries, founder and CEO of FRT, about how hybrid metrology is shaping multi-sensor metrology tools for improved measurement precision and the challenges facing metrology for MEMS and advanced packaging.

Plus, check out the latest blogs from the System-Level Design and IoT, Automotive & Security newsletters:

Editor In Chief Ed Sperling argues that shrinking features isn’t the only way forward.

Technology Editor Brian Bailey questions whether you have what it takes to moderate a panel discussion.

OneSpin’s Tom Anderson observes that industry initiatives are critical factors for processor family success.

Synopsys’ Youngsoo Lee warns that while SiPs consisting of SoCs and stacked HBMs are promising for AI, HPC and 5G, noise poses a challenge.

Mentor’s David Burnette digs into using high-level synthesis with IP libraries and toolkits to speed hardware accelerator development.

Cadence’s Frank Schirrmeister envisions a whole new level of systems design for the technologies of the future.

eSilicon’s Mike Gianfagna reveals Google Cloud’s pitch, from cloud computing for chip design to AI for whales and exoplanet discovery.

UltraSoC’s Jo Windel summarizes DAC’s major themes: IoT security, artificial intelligence and cloud EDA.

Aldec’s Zibi Zalewski explains why SoC hybrid co-emulation for verification of hardware and software is so important today.

Editor in Chief Ed Sperling finds a slowdown in Moore’s Law and the rise of new markets are creating a boon for security vendors.

Rambus’ Ben Levine warns that increased complexity practically guarantees that hardware vulnerabilities will continue to be unknowingly introduced.

Flex Logix’s Geoff Tate explains how to comparison-shop for inference accelerators to find the best throughput for the money.

Siemens’ Dan Scott and consultant Ulrike Hoff explain why getting the wiring harness right is a vital part of reducing vehicle weight and cost.

Coventor’s Benjamin Vincent points to why predicting outcomes of processes and defining process variation control improvements can save both time and money.