Blog Review: Mar. 12

Cadence’s P. Saisrinivas explains the relationship between drive strength and cell delay and why it is key to choose the appropriate drive strength to meet timing constraints while minimizing power and area.

Siemens’ Daniel Berger and Dirk Hartmann tackle the readout problem of accurately measuring the state of a quantum system after it has undergone a quantum computation, which becomes increasingly difficult as the number of qubits in a quantum computer increases.

Synopsys’ Igor Markov and Vincent van der Leest point out the differences between quantum cryptography, which uses the principles of quantum mechanics to secure communication, and post-quantum cryptography, which uses classical computing algorithms that are resistant to attacks from quantum computers.

Arm’s Virginia Cangelosi takes a complex pipeline of five different ML models that is able to translate songs from English to Mandarin and ports it to Android, with insight on key design choices to facilitate the process.

Keysight’s Nancy Friedrich highlights current areas of 6G research that aim to prove the viability of new spectrum allocations between 7 and 24 GHz, sub-terahertz bandwidths, network topologies that include non-terrestrial networks, reconfigurable intelligent surfaces, and the integration of AI/ML.

Ansys’ Wim Slagter checks out how GPUs can improve mechanical simulation performance, particularly for models with complex geometries, refined meshes, or high degrees of freedom that spend a substantial portion of the simulation time in a direct or iterative solver, and provides some tips on selecting the right GPU.

Rambus’ Cristian Boian finds that the switch to quantum-safe algorithms requires significant changes to security protocols like IPsec.

SEMI’s Pushkar Apte, Melissa Grupen-Shemansky, and IBM’s Jim Sexton focus on building pre-competitive collaboration that breaks through silos and explores system-level solutions to radically improve the energy efficiency of AI computing.

Plus, check out the blogs featured in the latest Automotive, Security & Pervasive Computing, Test, Measurement & Analytics, and Systems & Design newsletters:

Technology editor Brian Bailey suggests risk and fear go hand in hand within the semiconductor industry, and reducing them requires a balance against time and cost.

Technology strategy advisor Geoff Tate finds that an open, plug-and-play chiplet ecosystem still faces significant hurdles in interconnect standardization and packaging.

Onto Innovation’s Jiangtao Hu examines the benefits of integrating DUV spectroscopic ellipsometry with laser ellipsometry for gate oxide metrology.

Synopsys’ Faisal Goriawalla explains custom HBM and how integrating the functionality of the HBM base die into a logic die provides greater flexibility and additional control.

Siemens’ Marc Hutner digs into diagnosis-driven yield analysis and how it can uncover previously unknown systematic issues, reducing physical failure analysis cycle time.

Teradyne’s Jeorge Hurtarte finds that co-packaged optics require hybrid testing systems, with reliable alignment techniques that can handle both electrical and optical signals simultaneously.

Advantest’s Ira Leventhal explores the diverse class of AI chips and contends that test-flow stages must become dynamically adaptable with real-time decision-making.

Siemens’ John Muirhead extols the benefits of verifying layout integrity, ensuring IP placement accuracy, and validating critical symmetry requirements early in the design flow.

Imagination’s Eleanor Brash looks at the auto industry transformation around software-defined vehicles, user interfaces, assisted and autonomous driving, and heterogeneous systems and chiplets.

Rambus’ Adiel Bahrouch explains how heterogeneous SoC architectures complicate security implementation and integration efforts.

Cadence’s Steve Brown digs into autonomous robots and their potential role in space, helping with resource mining, data collection, and infrastructure construction.

Synopsys’ Faisal Goriawalla explores the unique challenges of ensuring multi-die quality and reliability, and why interconnect monitoring, test, and repair are crucial.

Infineon’s Sijia Zhang illustrates the key role of traction inverters in maximizing the range and performance of heavy-duty electric vehicles.

Siemens EDA’s Todd Burkholder, Wael Abdelaziz Mahmoud, Tom Fitzpatrick, Vishal Baskar, and Mohamed Nafea show how to create reusable and adaptable verification scenarios across multiple platforms.

Cadence’s Subash Peddu digs into HBM subsystems and why every fractional increase in performance has a multiplier effect on overall AI hardware performance.

Keysight’s Emily Yan finds that rapid AI innovations are putting unprecedented strain on data center networks, with issues around interconnects, high costs, and validation.

Synopsys’ Shekhar Kapoor expects that advancements in low-latency interconnects, manufacturing processes, and design tools will enable a proliferation of 2.5D and 3D designs.

Arteris’ Rick Bye details the benefits of Smart NoCs, including the ability to automatically generate, optimize, and verify interconnects with minimal manual effort.