Blog Review: May 1

Synopsys’ Melissa Kirschner questions whether a unified standard for safety-related code development will be enough to secure connected cars as MISRA and AUTOSAR merge C++ guidelines.

In a podcast, Mentor’s Brent Klingforth and John McMillan share questions and answers about rigid-flex PCB design, including the value of incorporating flexible circuits and the key challenges faced when doing so.

Cadence’s Paul McLellan listens in on the beginning of SEMICON China and considers what future the semiconductor industry will hold for the country.

A Rambus writer describes several recent hacks of connected vehicles, the threats they may face in the future, and why security by design is necessary to prevent them.

SEMI’s Serena Brischetto chats with Andy Collins of the Quantum Technology Enterprise Centre on developing a workforce for emerging technologies and helping academics make the jump to founding businesses.

ANSYS’ Vishal Ganore points to a free, online course available to anyone wanting to learn how to use the company’s engineering simulation software.

Intrinsic ID’s Marten van Hulst takes a look at how SRAM Physically Unclonable Functions (PUF) can provide a physical root of trust and how they can be used on conjunction with Arm’s TrustZone.

Intel’s Ron Wilson considers whether the use of virtual personal shoppers enabled by machine learning and AR could help revitalize brick-and-mortar retailers by creating more personalized experiences for shoppers.

And don’t miss the blogs featured in last week’s System-Level Design newsletter:

Editor In Chief Ed Sperling explains why the next big thing is unnerving tech giants and pushing design in new directions.

Technology Editor Brian Bailey describes verification as the process of comparing two models in a systematic manner to locate differences, but it always requires two models.

OneSpin’s Sergio Marchese warns that IC development steps are vulnerable to malicious insertions that may compromise system security.

Mentor’s Sherif Hany argues that it’s necessary to merge physical and electrical information to determine design rule compliance.

Synopsys’ Thomas Andersen contends that choosing the correct approach is key to using machine learning in chip design.

Silexica’s Luis Murillo advises teams to tackle concurrency problems early or face increased costs and delays in verification.

Cadence’s Frank Schirrmeister observes that ecosystems aren’t just about processor architectures and foundries anymore.

UltraSoC’s Aileen Ryan argues that when it comes to ensuring product safety, siloed thinking is dangerous.