Multi-die challenges; PDN and jitter; DSPs for ToF; AI skills gap.
Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards.
Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers by using a 3D field solver and time-domain simulation.
Cadence’s Sriram Sharma Kalluri checks out time-of-flight (ToF) sensors for depth sensing and why DSPs are needed to turn the raw data into something useful.
Arm’s Khaled Benkrid finds that there’s a shortage of expertise required to effectively integrate and utilize AI technologies in the workforce, with many companies reporting a lack of skilled talent as a barrier to AI implementation, and looks at what’s needed to bridge the skills gap.
Keysight’s Anubhab Sahu explains invisible prompt injection attacks against LLMs, in which malicious instructions are hidden using special Unicode characters.
Ansys’ Laura Carter chats with John Patalak of NASCAR about designing the motorsport’s next generation car chassis for safety and how simulation helped balance vehicle chassis crash accelerations with intrusion prevention.
SEMI’s Sitong He learns how spin-on dielectrics can offer a cost-effective, scalable solution for micro-gap filling and high-performance dielectric films and about the current focus areas for new polymer research.
Plus, check out the blogs featured in the latest Low Power-High Performance newsletter:
Power architect Barry Pangrle looks at what’s new and noteworthy in TSMC’s aggressive technology roadmap.
Fraunhofer’s Benjamin Prautsch explains how improving parasitic estimation and enabling partial layout extraction earlier in the design process leads to better optimization.
Siemens’ Chandu Challapalli highlights the challenges associated with verifying power intent for complex devices.
Rambus’ Nidish Kamath digs into the latest HBM standard, which provides improved memory bandwidth, capacity, power efficiency, and reliability.
Quadric’s Steve Roddy discusses how bolting a matrix accelerator onto existing processor IP leads to long-term challenges for companies.
Arm’s Cornelius Maroa provides a step-by-step tutorial on how to deploy PyTorch on edge devices for fast, efficient inference close to where the data is generated.
Synopsys’ Lakshmi Jain and Wei-Yu Ma discuss why advanced testing methodologies and enhanced testing equipment are needed to ensure signal integrity, accuracy, and optimal performance in complex chip designs.
Cadence’s Sangeeta Soni examines the impacts of the release of the UALink 200G 1.0 Specification.
Ansys’ Mehru Singh and Tim Ebdon explains why sustainable products are key to a company’s success in design, manufacturing and sourcing, and consumer experience.
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