Blog Review: Nov. 10

Cadence’s Paul McLellan listens in as Malcolm Penn of Future Horizons explains key reasons behind the cyclical nature of the semiconductor industry and how the root of the current chip shortage problems goes back to before the pandemic.

Siemens EDA’s Ray Salemi continues investigating using Python for verification with a look at some UVM utilities and how they would be used in Python.

Synopsys’ Gordon Cooper points to some key neural network accelerator performance benchmarking considerations and tips and what to look for when selecting embedded processor IP for an AI SoC.

Arm’s Eddie Ramirez checks out how data processing units (DPUs) handle the behind-the-scenes work of cloud computing such as exacting and time-sensitive security tasks like packet inspection and hypervisor management.

Ansys’ Nathan Brindle shows how Oculii used modeling and simulation to optimize phased array radars for automotive applications, including analyzing various aspects of antenna hardware such as gain and loss.

Intel’s Ruchira Sasanka and Chuck Yount consider how software optimization can achieve the best performance using HBM, the three different memories modes where HBM can be exposed to software, and a few tips on best practices.

A Rambus writer explains hardware roots of trust along with key features of a programmable root of trust.

And don’t miss the blogs highlighted in the latest Automotive, Security & Pervasive Computing and Test, Measurement & Analytics newsletters:

Flex Logix’s Vlad Bronstein contends that both the ML model and the target hardware must be understood to get the most out of inference accelerators.

Rambus’ Bart Stevens points to the need for digitally signing and verifying all stages of the boot loading sequence.

Synopsys’ Marc Serughetti explains how virtual prototypes for vehicular electronic systems can help streamline fault injection and find bugs earlier.

Siemens EDA’s Keith Felton and STMicroelectronics’ Cristina Somma show how to investigate and predict early electrical performance to drive automotive package development and selection.

Cadence’s Krunal Patel looks at key features required for time-sensitive, mission-critical, and deterministic latency requirements of the auto industry.

Xilinx’ Nick Ni explains how major gaps hinder AI algorithm proof-of-concepts from becoming real hardware deployments.

Onto’s Benoit Ravot shows how FTIR modeling delivers metrics based on materials’ bond types for compositional process control.

Siemens’ Jayant D’Souza lays out an alternative to the standard fault isolation techniques for both low-volume test vehicles and product ramp.

Advantest’s Philip Brock and Louis Benton, Jr. and Microchip’s Jonvyn Wongso reveal that each module in a keyless entry fob poses specific testing challenges and restrictions.

Synopsys’ Steve Pateras looks at how silicon lifecycle management is extending into bring-up and in-field operation.