Blog Review: Nov. 6

Cadence’s Satish Kumar C explores how the Deferrable Memory Write transaction type in PCIe and CXL can improve latency, efficiency, and performance by delaying certain memory write operations during system bus congestion or until other priority tasks are complete and highlights implementation and verification challenges.

Synopsys’ Daryl Seitzer and Rahul Thukral point to magnetoresistive RAM (MRAM) and resistive RAM (RRAM) as two emerging embedded memories that can provide the density, capacity, and scalability for modern processing requirements and highlight the key applications where each shines.

Siemens’ John McMillan warns that 3D-IC is not a simple extension of existing packaging solutions but creates a whole new set of multiphysics integration considerations that require disparate domains across thermal, mechanical, reliability, test, and core semiconductor design to seamlessly collaborate.

Ansys’ Caty Fairclough considers the roles that sensing and perception technologies play in autonomous systems operating in the aerospace and defense industry and the challenges of ensuring that designs can function optimally even in many types of platforms.

Keysight’s Richard Duvall provides a basic primer on EDA for PCB and IC design, including key steps in the  design workflows and how they differ.

Arm’s Rob Elliott, Fredrik Knutsson, and Mark Quartermain offer a guide on using ExecuTorch to deploy PyTorch models on edge devices using the Ethos-U85 NPU, enabling developers to start model and edge AI application development months before the platforms arrive on the market.

SEMI’s Serena Brischetto chats with Thorsten vom Stein of Merck about challenges in the digitalization of chemical process design for semiconductor materials manufacturing and the importance of linking material manufacturing process to the process parameters of tools in the fab.

Plus, check out the blogs featured in the latest Systems & Design newsletter:

Siemens EDA’s John Golding shows how to use a signal integrity simulator to find the optimal interconnect topology and termination for a given situation.

Synopsys’ Aparna Tarde digs into die connectivity, splitting, and attachment for AI applications, ensuring interoperability, low latency, and real-time data movement.

Arteris’ Andy Nightingale looks at the benefits of physically-aware and domain-aware NoCs, including low power, high performance, and scalability.

Alphawave Semi’s Shivi Arora and Sue Hung Fung explain why 6G will require new RF designs and chipsets capable of handling much larger amounts of data.

Cadence’s Nayan Gaywala delves into HPC subsystems and why CPU cores need to access shared data in an atomic fashion in a multi-core environment.

Keysight’s Allison Freedman outlines steps to enhance cyber defense training and why it’s essential to create realistic models of mobile networks.

Eliyan’s Ramin Farjadrad takes stock of what’s needed to consistently move data at speeds required for AI systems.