Blog Review: Oct. 23

Cadence’s Sanjeet Kumar introduces the message bus interface in the PHY Interface for the PCIe, SATA, USB, DisplayPort, and USB4 Architectures (PIPE) specification, which provides a way to initiate and participate in non-latency-sensitive PIPE operations using a small number of wires.

Siemens’ Dennis Brophy argues that the recently published Portable Test and Stimulus Standard (PSS) 3.0 will revolutionize the way system-level design and verification engineers approach their work by offering a host of new features and enhancements designed to boost productivity and efficiency.

Synopsys’ Steffen Ragnow provides an overview of the optical design workflow for an automotive headlamp using total internal reflection (TIR) lenses, along with design options with TIR devices for high and low beam applications.

Keysight’s Hieng Ling Tie explains the multiple communication modes under the Vehicle-to-Everything (V2X) umbrella, the benefits and drawbacks of Dedicated Short-Range Communication (DSRC) versus Cellular Vehicle-to-Everything (CV2X), and why testing V2X systems is critical.

Ansys’ Srikanth Adya notes that while ‘safety at any cost’ is a nice ideal, reduced developmental timetables and budgetary limitations mean that engineers may be forced to prioritize safety aspects thought to reduce accident severity or to seek more cost-friendly strategies, such as the phased implementation of safety features.

Arm’s Madhusudan Rao lists many of the top considerations involved when building products that are functionally safe for increasingly complex automotive systems.

In a blog for SEMI, Silicon Assurance’s Pavani Jella warns that evolving cyber threats and sophisticated attacks make it essential for vendors to integrate advanced security measures into their design and development workflows for IP and SoCs.

Plus, don’t miss the blogs featured in recent newsletters:

Technology editor Brian Bailey asks if EDA is meant to react to the needs of the industry, or anticipate its needs and develop ahead of the curve.

Siemens’ Sara Khalaf shows how symmetrical structures help ensure consistent electrical behavior in analog and RF designs.

Quadric’s Steve Roddy discusses the need to minimize system power consumption and data access latency in AI inference devices.

Fraunhofer IIS/EAS’ Volkhard Beyer and Dirk Mayer outline ways to optimize IoT device lifecycles and reduce waste.

Rambus’ Tim Messegee digs into the latest graphics memory solutions for AI-enabled edge and endpoints.

Synopsys’ Lakshmi Jain and Wei-Yu Ma extol the bandwidth improvements in 3DIO versus 2.5D.

Arm’s Ayaan Masood recounts how an open-source neural network was used for real-time mobile inference.

Cadence’s Mark Seymour explores different cooling options, why they’re needed, and how to test them.

Ansys’ Thomas Lejeune looks at the performance and cost competitiveness of a plug-and-play cloud platform.

Onto Innovation’s Keith Best digs into an assortment of through-glass interconnect defects.

Synopsys’ Ash Patel explains how a range of sensors help gather meaningful data at each stage of the device lifecycle.

proteanTecs’ Noam Brousard shows how real-time health monitoring (RTHM) of hardware can detect low-latency failures at the component level and allow for faster and more accurate intervention.

Teradyne’s Jeorge Hurtarte digs into test strategies to accommodate advanced packaging and chiplets, including dynamic test coverage as a bridge between ATE and SLT.

Advantest’s Shinji Hioki and Ken Butler outline the challenges at each stage of semiconductor manufacturing and how meaningful ML applications can help with business needs.

Rambus’ Tim Messegee looks at a protection model that covers the entire the data lifecycle, whether Data-at-Rest, Data-in-Motion or importantly Data-in-Use.

Cadence Design Systems’ Kunal Chhabriya shows how to prevent side-channel attacks based on attacker analysis of information included in headers.

Infineon’s Diana Car explains how to enable more compact and efficient traction inverters for hybrid-propulsion trains.

Siemens’ Suprio Biswas explores two methods for setting up secure connection: the classic symmetric flow compared to an asymmetric flow where each device has its unique key.

Synopsys’ Rich Collins explains how a customized processor implementation helps meet the specific needs of a target application.