Blog Review: Oct. 30

Synopsys’ Frank Schirrmeister argues that hardware-assisted verification techniques like emulation and prototyping are essential to help engineers improve design behavior to manage complexity and ensure systems function seamlessly in real-world applications.

Siemens’ Stephen V. Chavez finds that ultra high-density interconnect (UHDI) has changed the design and production of PCBs to enable high-density circuitry that can fit into compact devices without compromising performance or functionality and suggests that the continued development of 5G, AI, and IoT will motivate PCB designers to push the boundaries of what UHDI can achieve.

Cadence’s Asad Makandar shows how to automate the generation of PCB documentation, including fabrication and assembly drawings, to reduce the time and effort invested in developing and maintaining multiple documents manually.

Ansys’ Maxim Ershov drills into the root causes of errors in electrostatic discharge (ESD) verification, which can result in parasitic extraction tools on standard post-layout netlists sometimes yielding calculated resistances that are higher or lower than actual values by a factor of up to 100 times.

Keysight’s Brian Whitaker provides some tips on selecting a signal generator based on the phase noise requirements of a specific application, including factors like internal architecture, type of oscillator, internal and external frequency references, and tradeoffs in switching speed and optimization for close-in or far-out offsets.

Arm’s Ashok Bhat shows how to use the KleidiAI library to improve PyTorch inference performance on Arm Neoverse and explains the difference and potential speedups in eager and graph modes.

SEMI’s Justin Harris and Bia Hamed and Climate Equity Collaborative’s Marley Hauser call for a program that brings together youth empowerment, workforce development, and climate action to provide resources that enable K-12 students to engage in sustainability-focused STEM projects, even in low-resource schools.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Synopsys’ Kevin Lucas and James Ban explain how additional process variation creates challenges at the boundary between two mask exposures in high-NA EUV.

Lam Research’s QingPeng Wang shows how to determine the capacitance behavior of a MOM device without lengthy, expensive silicon-based testing.

The eBeam Initiative’s Jan Willis highlights a discussion on multi-beam mask writers and curvilinear masks held at the 2024 SPIE Photomask and EUV conference.

Amkor’s Curtis Zwenger contends that embedding the redistribution layer in the organic dielectric prevents seed layer undercut issues.

Brewer Science’s Jessica Albright digs into collective die-to-wafer bonding and how it enables higher integration density.

Silicon Assurance’s Pavani Jella, in a SEMI guest blog, spells out the need for deeper verification processes and tools to support secure-by-design principles.