Blog Review: Sept. 2

When it comes to cars, manufacturers may be adding too many features too fast, says Mentor’s John Day. Up to half of the features may never get used either because they aren’t useful or they are too complex.

Cadence’s Christine Young sat down with Neeti Bhatnagar, a software engineering group director to discuss the challenges and rewards of working in a distributed, cross-functional team, the increasing importance of software-hardware debug in SoC design, and how debug needs to advance.

Ansys’ Justin Nescott sees a glimmer of hope for old fashioned pen and paper, but only when aided by a lot of technology, and a bunch of other exciting technologies.

Looking for some articles to read? ARM’s Brian Fuller points you in some good directions, including an analysis of smart watches from a UCLA student.

Interested in skyscraper 3D NAND memory? Applied’s Brad Howard reports on a panel discussion from the Flash Memory Summit.

The adoption of DDR4 continues according to Rambus’ Aharon Etengoff and Intel projects it will be shipping more DDR4 than DDR3 for desktops by mid 2016.

For more good reads, check out the blogs featured in last week’s System-Level Design newsletter:

Editor in Chief Ed Sperling questions whether chipmakers will be able to grab a bigger slice of the pie as the semiconductor industry consolidates.

Technology Editor Brian Bailey contends that just because logic shows something to be 100% right doesn’t mean it’s the correct answer.

Synopsys’ Tom De Schutter observes that electronic giants have finally caught on to what makes a big difference.

Aldec’s Louie De Luna asks whether you can bet your life on your designs.

Arteris’ Kurt Shuler points to greater productivity, lower power, smaller die sizes and higher bandwidth in mature geometries as Moore’s Law slows.

Cadence’s Frank Schirrmeister notes that abstraction needs to be applied consciously, and users need to be aware of its shortcomings.

Mentor Graphics’ Nicolas Williams and Jeff Miller examine the conflicting needs of IoT edge devices—inexpensive but powerful design tools.

eSilicon’s Mike Gianfagna has a new calendar entry when everything changes.