Building A Better CMOS FET

By Barry Pangrle
SEMICON West was held last week in San Francisco and I had the opportunity to attend the Emerging Architectures session. Serge Biesemans, vice president of process technology at Imec, gave a nice overview presentation on FinFETs. From a power and performance standpoint, we’ve seen some early pre-production information released from Intel that I briefly discussed here. Serge’s presentation also contained some of the previously published information from Intel as well as some interesting material about other aspects of FinFETs.

One of the points made in Serge’s presentation is that there are a host of new device architectures are aimed at fully depleted channels for better short-channel control (with FinFETs just being one of them). Ali Khakifirooz, ETSOI lead device engineer for IBM, described some planar devices that also have fully depleted channels. (By the way, ETSOI stands for Extremely Thin Silicon On Insulator.) As transistors get smaller, the channel formed between the source and drain gets shorter. And partly due to an effect known as Drain Induced Barrier Lowering (or DIBL for short), sub-threshold leakage gets worse. Typically, gate leakage also gets worse as the insulator between the gate and the channel gets thinner. High-K Metal Gate (HKMG) processes, first introduced into mass production by Intel at their 45nm node, have proven superior to the older polysilicon SiON processes and are now being widely adopted by other foundries at the 28nm node.

There’s a history of technologies running up against a “power wall” as they mature. A diagram from a Stanford EE319 presentation used by Raj Jammy, vice president of materials and emerging technologies at SEMATECH, in his presentation illustrates how Bipolar logic gave way to CMOS and how the power issues in CMOS, culminating with the Intel Pentium IV Prescott, have forced device engineers to innovate new ways to keep CMOS moving forward. For those who were around before the wide adoption of CMOS, you may also remember a brief period of time when nMOS was dominant but gave way relatively quickly to CMOS based on energy-efficiency.

Serge also pointed out in his presentation that as fins get thinner, there is less control over the threshold voltage (Vt) of the devices. Another way to control the threshold voltage is through work-function tuning of the metal gate process. This would seem to imply the need for the availability of multiple work-function gate types in order to provide a multi-Vt solution.

The SOI crowd is rather quick to point out that if a thin insulating oxide layer is used, the threshold voltage can be controlled by using a fourth terminal to bias the substrate on the “backside” of the insulator. Prof. Andrzej Strojwas from CMU asked about the possible impact of having only one Vt available with a FinFET process, and if such a process would perhaps be better suited for high-performance processors but maybe less so for other SoC applications.

On top of all of this, a relatively small company based in Los Gatos, Calif., recently announced it has developed a planar CMOS process that uses a Deeply Depleted Channel (DDC). SuVolta claims its process is very similar in terms of implementation complexity to a standard bulk planar CMOS process, yet yields results that are competitive with fully depleted architectures. If SuVolta’s claims are sustained through real production silicon, there may still be a bit more life left in bulk planar CMOS. It will be exciting to watch how these different device architectures play out in the market.

–Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics.