Analysis Of Multi-Chiplet Package Designs And Requirements For Production Test Simplification

By Vineet Pancholi - 21 Nov, 2024 - Comments: 0

In recent years there has been a sharp rise of multi-die system designs. Numerous publications targeting a large variety of applications exist in the public domain. One presentation [2] on the IEEE’s website does a good job of detailing the anecdotal path of multi-die systems by way of chiplet building blocks integrated within a single package [2]. The presentation includes references to a ha... » read more

Revolutionizing IC Packaging With High-Density RDL Technology

By Curtis Zwenger - 24 Oct, 2024 - Comments: 0

The demand for high-performance devices, particularly in AI, HPC, and data centers, has surged dramatically in the ever-evolving landscape of integrated circuit technology. This demand has been further accelerated by the COVID-19 pandemic, pushing the boundaries of silicon technology to its limits. Enter Amkor’s S-SWIFT, a packaging solution designed to address these challenges and revolution... » read more

Novel Molded FCBGA Package Platform For Highly Reliable Automotive Applications

By InRak Kim - 19 Sep, 2024 - Comments: 0

The conventional flip chip ball grid array (FCBGA) package platform has wide industry usage and provides high electrical performance. However, as high performance requirements increased, it encounters significant challenges. FCBGA packages frequently encounter underfill cracks after long term reliability or harsh reliability test conditions for automotive devices. Figure 1 shows the typical und... » read more

Current Characterization Of Various Cu RDL Designs In Wafer Level Packages (WLP)

By JeongMin Ju - 15 Aug, 2024 - Comments: 0

Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and widths of 5-20 µm are used for high current sourcing. In this case, the temperature of the Cu RDL metal line increases due to the Joule heat generated when current passes through the metal line. If a... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging

By Heejun Jang - 23 Jul, 2024 - Comments: 0

With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Development Of Capacitance Measurement Unit For A System Level Tester

By BeomSeok Kim - 20 Jun, 2024 - Comments: 0

By BeomSeok Kim, SeongHwan Kim, Unki Kim, SeongBeom Cho, DongHo Seo, and SangHun Yun In back-end semiconductor processing it is important to improve the performance of semiconductors due to the limitations of miniaturization in front-end processes. To achieve this goal, the industry continues to invest in back-end processing and competition is fierce in advanced technology of back-end proces... » read more

Package Assembly Design Kits: The Future Of Advanced Package Design

By Ruben Fuentes - 23 May, 2024 - Comments: 0

Why should there be an interest in Package Assembly Design Kits (PADK) today? For the most part, it is due to the advancement in the accumulation of files forming the PADK now offering a customized heterogeneous design experience that optimizes the device's intended package performance with complete connectivity verification, DRC, and assembly validation. Another primary reason is the ongoing f... » read more

Powering The Automotive Revolution: Advanced Packaging For Next-Generation Vehicle Computing

By Prasad Dhond - 18 Apr, 2024 - Comments: 0

Automotive processors are rapidly adopting advanced process nodes. NXP announced the development of 5 nm automotive processors in 2020 [1], Mobileye announced EyeQ Ultra using 5 nm technology during CES 2022 [2], and TSMC announced its “Auto Early” 3 nm processes in 2023 [3]. In the past, the automotive industry was slow to adopt the latest semiconductor technologies due to reliability conc... » read more

Package Integrated Vapor Chamber Heat Spreaders

By Sanghyuk Kim - 21 Mar, 2024 - Comments: 0

With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging

By JiHye Kwon - 18 Jan, 2024 - Comments: 1

The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

category: Chip, Package, System

category: IoT, Security & Automotive