Why All Nodes Won’t Work

A flood of new nodes, half-nodes and every number in between is creating confusion among chipmakers. While most say it's good to have choices, it's not clear which or how many of those choices are actually good. At issue is which [getkc id="43" kc_name="IP"] will be available for those nodes, how that IP will differ from other nodes in terms of power, performance, area and sensitivity to a v... » read more

IP And Power

[getkc id="108" kc_name="Power"] is quickly becoming a major differentiator for products, regardless of whether they are connected to a wall outlet or dependent on a battery. At the same time, increasing amounts of a chips content comes from third-party [getkc id="43" kc_name="IP"]. So how do system designers ensure that the complete system has an optimal power profile, and what can they do to ... » read more

New Issues In Advanced Packaging

Advanced packaging is gaining in popularity as the cost and complexity of integrating everything onto a planar SoC becomes more difficult and costly at each new node, but ensuring that these packaged die function properly and yield sufficiently isn't so simple. There are a number of factors that are tilting more of the the semiconductor industry toward advanced [getkc id="27" kc_name="packag... » read more

Wireless Charging Creeps Forward

It's well known that electricity can travel long distances through the air, but expanding beyond the boundaries of a wire has never seemed a practical or reliable way to power delicate electronics. In fact, wireless power has been widely available for years. Whether this approach will be used to extend battery life isn't entirely clear. But it is attracting renewed attention as the balance b... » read more

Chip Aging Accelerates

Reliability is becoming an increasingly important proof point for new chips as they are rolled out in new markets such as automotive, cloud computing and industrial IoT, but actually proving that a chip will function as expected over time is becoming much more difficult. In the past, reliability generally was considered a foundry issue. Chips developed for computers and phones were designed ... » read more

New Thermal Issues Emerge

Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

Pushing Performance Limits

Trying to squeeze the last bit of performance out of a chip sounds like a good idea, but it increases risk and cost, extends development time, reduced yield, and it may even limit the environments in which the chip can operate. And yet, given the amount of margin added at every step of the development process, it seems obvious that plenty of improvements could be made. "Every design can be o... » read more

Turning Down The Voltage

Designers of large, advanced-node SoCs are grappling with a number of pressures in the quest to achieve the optimal performance and power of their designs. This has turned into a challenging balancing act between using less power, especially for consumer technologies, while also providing the same or greater performance and increased functionality. [getkc id="108" kc_name="Power"] and perfor... » read more

Data Buffering’s Role Grows

Data buffering is gaining ground as a way to speed up the processing of increasingly large quantities of data. In simple terms, a data buffer is an area of physical [getkc id="22" kc_name="memory"] storage that temporarily stores data while it is being moved from one place to another. This becomes increasingly necessary in data centers, autonomous vehicles, and for [getkc id="305" kc_name=... » read more

Turning Down The Power

Chip and system designers are giving greater weight to power issues these days. But will they inevitably hit a wall in accounting for ultra-low-power considerations? Performance, power, and area are the traditional attributes in chip design. Area was originally the main priority, with feature sizes constantly shrinking according to Moore's Law. Performance was in the saddle for many years. M... » read more

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