CES—The Morning After

CES 2010 was quite a party, coming off the misery of 2008-2009. Tablets were everywhere, smart phones are racing ahead, the PC is dead. Our industry is reinventing the electronic experience yet again. I saw one forecast of a $1 trillion consumer electronics market within a few years. This is heady stuff. It restores hope not only in the future of electronics but also the possibility that electronics growth may help to power the global economy back to solid growth. It makes you proud to be an engineer (with perhaps a little queasiness over accelerating an electronically connected and personally disconnected society).

And yet… This is not easy money. Consumers are fickle, they have a finely tuned sense of value, and everyone with a stake in electronic products wants a piece of their wallet. Products must be feature-rich, adaptable to a wide range of markets and quickly re-spun to add more features or different form factors. If you think these devices already have all the features they need, think about Google “near-field communications” or “energy harvesting.” This is not a market for long-term enterprise/catalog product teams. This is pure survival of the fittest, and fit means fast and adaptable. Check out this article if you want more Darwinian analogies.

This consumer market is not just another turn of the screw on “chips are getting bigger, time to market is shrinking.” This is qualitatively different. The size of the prize and the level of competition dictate we will be paid only for features. The premium for development, and time to market for a new feature introduction (especially if you are not first to market with that feature), can be six months or less. In this new reality it is essential to drive cost and risk out of product development. Handcrafted, integration-focused register transfer level (RTL) design commands no differentiated value and increases cost, risk and delay. High-level synthesis has its place at the block/algorithm level but is not the solution to the integration problem. Think Dell—fast feature assembly needs pre-defined, well-characterized reusable blocks assembled as automatically as possible with robust hookup checks to reduce (not eliminate) debug cycles in verification.

Several thought leaders—including Texas Instruments and STMicroelectronics among IDMs, and Samsung and Canon among system OEMs—already have re-engineered their design processes around exactly this approach. They have organizations that produce, maintain and qualify IP (and inspect incoming IP), platforms on which they can quickly spin variants and automated assembly tools and dedicated integration teams to reduce cycle time to handoff RTL. But this is not a game only for the rich or for major corporate initiatives. Small companies and teams are achieving the same level of productivity using the same methods, scaled down. All it takes is a willingness to set the process and tools in place, to forgo tweaking (starting from someone else’s RTL, and tweaking is not re-use) and to accept that it’s now all about execution in delivering platform variants.

The party was fun and the opportunity is tremendously exciting, but it’s only for those who are ready to change their game.