Keeping clock domains straight is getting tougher, causing late-stage ECOs and re-spins.
In late September, I blogged about the results of the 2012 DAC survey on CDC bugs, X propagation, and timing constraints by Real Intent. Now for those of you who don’t remember what CDC means, it is an acronym for clock domain crossing.
In modern SoCs, the number of different clock domains can easily exceed 100, due to the integration of different blocks and IP, each with their own clock. Not only do the clocks run at different rates, but they also can change in frequency based on dynamic changes in the power mode for each block. Signals that cross from one domain to another asynchronously can suffer from metastability and cause undefined or incorrect behavior—bugs. Because of the number of clock domains has expanded dramatically, and SoCs now exceed 400M gates in complexity, not only must CDC be analyzed, but it also has become a sign-off requirement. Dr. Roger Hughes gives an excellent overview of these challenges in his YouTube video interview.
Our 2012 DAC survey showed that 62% of the respondents said that CDC bugs resulted in late stage ECOs or product re-spins. In 2011, this was slightly higher at 65%. These bugs are affecting design schedules and design teams need to do CDC verification to have success. What are the other 28% doing? Some design teams tell us that their design methodology is immune to CDC issues. We think this is not typical for fabless semi design teams.
Chip Design Magazine also has been running a poll entitled, ‘Have you had CDC bugs slip through resulting in late ECOs or chip respins?’ If you go to Chip Design and scroll half-down the page and on the left side you will see this:
I have been monitoring this poll for a while and there has not been a lot of recent activity. Feel free to go there and cast your vote. Here are the results so far:
It is interesting to note that 40% have experienced a re-spin, 30% have had a late ECO, and 28% have had no trouble at all (very similar to the Real Intent poll).
What can we conclude? CDC analysis and verification is a pain point for SoC designers. More than two-thirds need a better CDC solution. To find out more, check out our white paper: Challenges in Verification of Clock Domain Crossings.
Want your vote to be recognized? Comment on this blog or go to Chip Design and scroll down to cast your vote.
Best wishes for happy holidays!
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[…] the pain points designers are feeling. I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing […]
[…] the pain points designers are feeling. I last reported to you, a year ago, in the blog article Clocks and Bugs, where I focused on clock-domain crossing (CDC) errors causing […]