Introducing GICv5: Scalable And Secure Interrupt Management For Arm

As Arm-based infrastructure continues to scale across markets, demands on system components increase. This can mean more interrupts, or signals from hardware/software to a processor to pause a task and handle another. Arm’s Generic Interrupt Controller Architecture (GIC) helps manage the communication between devices and processors efficiently. It makes sure the right processor handles the right task at the right time, with important tasks getting priority. Today, we are excited to introduce GICv5.

GICv5 is a rearchitected design that meets the demands of modern computing. It also enables simpler hypervisors with a smaller trusted computing base (TCB), improved power management, and enhanced support for system partitioning.

Scaling to larger systems

Modern systems are scaling to core counts in the hundreds, which is a significant leap from the configurations GICv3 and GICv4 were designed for. Previous GIC architectures face integration bottlenecks when deployed in large-scale systems. Challenges like arbitrary limits on wired interrupts and the need for global memory-mapped IO (MMIO) registers create complexity in both hardware design and software programming.

GICv5 addresses these challenges directly, delivering:

• No limits on the number of wired interrupts.
• No globally synchronized MMIO registers.
• A redesigned programmer’s model that supports systems from one to hundreds of cores.
• Dynamic scaling of the number of interrupts.

Virtualization performance

With GICv3, most interrupt-related operations (handling, configuration, and inter-processor signals) requires a trap to Exception level 2 (EL2), the hypervisor level. This added latency and polluted both caches and predictors. GICv4 made meaningful progress with direct injection of Message Signaled Interrupts (MSIs) and Inter-Processor Interrupts (IPIs), especially with GICv4.1, delivering significant performance improvement in interrupt-heavy workloads and in IPI-focused use cases.

With GICv5, virtualization overhead is eliminated, meaning:

• All interrupt types now support direct injection.
• No hypervisor traps are needed for sending or receiving IPIs.
• Interrupt configuration can be read and updated without trapping to EL2.

These benefits make virtualization-based system partitioning possible with GICv5. This is a promising technology for consolidating real-time sensitive workloads with more complex workloads on a single chip by leveraging virtualization. GICv5 allows a real-time OS to run side-by-side with a rich OS, for example providing vehicle control functions and in-vehicle entertainment on the same SoC.

GICv5 and Arm Confidential Compute Architecture

With GICv3 and GICv4, interrupt virtualization requires hypervisor intervention, and since GIC emulation for Realms is done in the Normal world hypervisor, the cost of a trap is higher than for regular VMs. This adds overhead and creates an undesirable reliance on the untrusted hypervisor for critical interrupt functionality.

GICv5 does not require hypervisor intervention for common interrupt operation and therefore allows implementing GICv5 emulation and support code in the Realm Management Monitor (RMM) with a small impact on the TCB. This enables:

• Direct interrupt delivery to Realms, without EL2 involvement.
• Realms and non-Realm VMs now experience identical interrupt handling.
• The Realm owns the interface to the GIC, including the memory that holds its interrupt state.
• With RME Device Assignment (RME-DA), interrupts can be end-to-end confidentiality and integrity protected.

Hardware and software impacts

GICv5 introduces significant changes to both hardware and software. The traditional Distributor and Redistributor are replaced by the Interrupt Routing Service (IRS), with a simplified ITS model and a new Interrupt Wire Bridge (IWB) to convert wired signals. The CPU interface is updated with new system instructions to improve interrupt handling and avoid traps to EL2. It also supports relaxed ordering using Arm’s memory model tools.

A new GIC Stream protocol ensures interoperability between CPU interfaces and IRS. While the programming model isn’t backward compatible, GICv5 includes a virtual CPU interface to support existing OSes in VMs. Arm will provide updated firmware, Linux/KVM support, and virtual platforms to accelerate development.

For more on GICv5: Visit Arm Developer