Introduction Of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard

Universal Serial Bus (USB) technology is the most popular connector in every computing device, but when it comes to embedded applications, where only a specific device function may be required, the architectural philosophy of the USB technology becomes inefficient.

One example could be USB cameras. With increasing user expectations of camera resolution and frame rates, the bandwidth constraints of USB 2.0 require today’s cameras to aggressively apply compression to fit within its bandwidth limitations. Even with compression, next-generation cameras will exceed the USB 2.0 bandwidth limitations.

If USB 3.x technology is used to address the bandwidth need, it is not an optimal solution for these camera devices because it is a symmetrical link offering the same bandwidth capacity to both downstream and upstream traffic. For a camera device, the bandwidth requirement is asymmetrical. A USB 3.x camera is not an optimal solution for embedded applications and is also not cost-effective as compared to USB2 devices.

This usage model reveals a technology gap in the platform I/O space, yielding an inflection point of opportunity. The eUSB2 Version 2.0 (eUSB2V2) is developed to deliver a scalable I/O technology specifically designed for inside-the-box (embedded) USB applications, optimizing for performance, power, and cost. It supports a low-voltage, power-efficient PHY with gigabit rates on a USB 2.0 architectural framework, i.e., half-duplex link and transactional protocol.

Topology

The eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals, such as embedded cameras, by adding significantly higher data rates to USB 2.0 while maintaining a low-voltage electrical interface. As eUSB2V2 is intended to support in-box applications in native mode, the physical channel is relatively simple, with both the host and the peripheral being inside the system’s physical boundary. An external cable or connector is not supported; however, one re-driver between the host and peripheral is allowed.

Key eUSB2v2 PHY features

• eUSB2V2 transfer rates:
  • HSSx-speed: Symmetric operation where the link is operating at 960Mbps to 4.8 Gbps in both transfer directions
  • Optionally, if symmetric 480Mb/s operation is desired, it shall be done via eUSB2 native mode
  • HSUx-speed: Asymmetric operation where the link is operating at 960 Mbps to 4.8 Gbps in the upstream direction and at 480 Mbps in the downstream direction
  • HSDx-speed: Asymmetric operation where the link is operating at 960 Mbps to 4.8 Gbps in the downstream direction and at 480 Mbps in the upstream direction
• Reduced bus turnaround time:
  • Only in-box applications are supported, minimizing peripheral interconnect propagation times
  • Enables shorter interpacket delays
• Increased maximum size of bulk packets from 512B to 1024B
• Enables more efficient isochronous transfers to improve transaction efficiency:
  • More than 3072B of isochronous packets may be transferred per service interval (SI)
  • Burst transactions are enabled for isochronous transfers, allowing the transmission of up to three data packets after a single IN or OUT token, thereby reducing the bandwidth requirement to n/3
  • If more than 1024B of isochronous data is transferred per microframe, then all data packets must be 1024B, with the remainder in the last packet
• Supports link power management LPM-L1 (L1) and Suspend (L2)
• eUSB2v2 implementation is based on UTMI 2.0 Parallel Mode
• Supports register access protocol (RAP) for eUSB2V2 peripheral or re-driver configurations
• Fully compatible with USB 2.0 base spec at the protocol layer
• No change to the USB 2.0 software programming model
• Not compatible with the physical layer defined by USB 2.0 or eUSB2
• Not compatible with standard USB 2.0 connectors defined by USB 2.0 and its derivatives

Cadence has a comprehensive Verification IP solution for the verification of various aspects of eUSB2 Version 2.0 (eUSB2v2), with capabilities provided to do a comprehensive verification of all features.