IP Power Models Enable Energy-Aware System-Level Design

Energy efficiency is one of the primary design metrics for heterogeneous multi-core mobile platforms, and the very real threat of dark silicon reinforces the fact that we must manage energy consumption in these platforms intelligently.

The way in which a platform is used absolutely determines how much energy it consumes, so we need to take a holistic approach to energy management. Furthermore, any power, energy and thermal analysis of the platform must be use-case or scenario driven and should include analysis under real software load. By understanding how the platform will be used and when and where it consumes the most power we can better optimize hardware architectures, develop energy efficient software, more efficiently partition functionality between software and hardware, develop and optimize system power management and direct the low power physical implementation of IP to ensure we satisfy the specific power and performance goals for the platform.

We continue to see power and performance trade-offs addressed at the IP level and the optimization of the physical implementation of an IP component to deliver energy efficient performance is obviously still required. However, if that component is then used inefficiently in the platform, our effort at the IP level is wasted. Therefore it is essential to optimize for energy efficiency at the system level. In addition, decisions made early in the platform development cycle will yield the greatest impact in terms of energy efficiency, so we need to shift-left in our approach to energy management to take advantage of system-level design techniques. This will enable us to achieve the significant gains in energy efficiency that we require.

Virtual prototyping is a methodology that enables this shift-left in approach to energy efficiency. A virtual prototype is an executable software model of a hardware system that simulates the hardware at a level that is relevant and can be used in both software development and in hardware exploration by abstracting away details of the hardware that are not important. Synopsys Platform Architect, Virtualizer and Virtual Development Kit (VDK) prototyping tools support this shift-left approach for early architecture design and software development, respectively.

This obfuscation of detail enables almost real time simulation of the platform. By annotating the simulation with power information we can gain valuable insight into the energy behaviour of the platform across a wide range of real world scenarios.

The visibility of component power behaviour is provided through the use of IP power models specifically created for use in system-level design environments.
An IP power model is an abstraction of the power behaviour of a component and provides specification of the supported component power states and power consumption data with flexibility in refinement, granularity and accuracy to support a variety of use cases.

There are three main parts to an IP power model: power states, associated power consumption data for static and dynamic power dissipation in each power state, and the power state activation conditions.

IP power models can be used at many levels of design abstraction and for various types of analysis. However, it is important to note that not all abstraction levels or types of analysis require the same accuracy or power state granularity within the power model. For example, when an IP power model is used within a virtual prototype for software centric power analysis the absolute accuracy of the power consumption data for each power state may not be as critical as it would be when used in SoC power estimation. For software-centric analysis, the software developer may simply be looking for an improving trend in the energy consumption of the code as it is developed rather than absolute consumption figures, whereas for SoC power, estimation of absolute power consumption data is likely to be of far greater interest.

Similarly, when power models are being used to help bring up system power management software, greater visibility into the various power states of the platform may be desired, which would require greater power state granularity in the power model.

Power states that are enumerated within an IP power model are defined to be sensitive to specific activation triggers within the simulation, and the diagram above shows how the concept works within Synopsys Platform Architect, Virtualizer and VDK simulation environments. Because these power models can be consumed by a variety of system-level design tools and used in many different types of analysis, these triggers or activation conditions can vary widely from specific port or signal transitions to process calls within software. This flexibility in activation provides significant advantages within the virtual prototype environment.

Power consumption data is provided for each enumerated power state in the power model through the use of power functions. These power functions are called, along with a set of associated parameters, and used to calculate the power consumption for the given power state. Both leakage and dynamic power consumption are modeled, with flexibility to provide a detailed breakdown on the power consumption as required (e.g. power consumption per voltage rail etc.).

Some of the parameters that are passed to these power functions from the environment are obvious (process, voltage, frequency, temperature etc.), but there are other design and run-time parameters that are passed, which we refer to as the power critical parameters of the IP. These are parameters that significantly impact the overall power consumption of the component such that their effect must be considered during simulation. These parameters include things such as bandwidth, refresh rate, cache hit rate etc.

IP power modeling for system-level design is currently being standardised as part of the IEEE 1801 “UPF 3.0” initiative, which is expected to be approved and released in 2015.