Big processor companies are making big bets on chips and they’d better get it right.
Power optimization is a system issue. How many times have you experienced your cell phone provider sending your phone an update and the battery lifetime then improving? The hardware team built in the hooks but there just wasn’t enough time to get the software together and tested before the product needed to ship, so the improved functionality shipped later. Well, that’s at least one advantage with software, but in the meantime the product is left to fend for itself while not quite firing on all cylinders. With the short product lifetimes for consumable goods like cell phones, that can mean a big impact on the product’s profitability.
Big processor companies make huge bets, whether it’s CPU or GPU or the very likely blurring of both. A quote that’s often attributed to a then-board member of a large processor company is, “Designing microprocessors is like playing Russian roulette. You put a gun to your head, pull the trigger, and find out four years later if you blew your brains out.” Power and multicore designs are now playing a big part in this equation. Trying to guess the right level of integration for a given technology node is challenging. The thinking is that putting more functionality on the same chip saves power. Certainly there’s the hope that not having to communicate off chip will be more energy efficient. Overreach, though, and you just might end up with a chip that’s really too big and complex to show efficiencies at the current node or it ends up coming to market too late to have the desired impact.
A couple of cases to consider:
At last year’s DAC, Bill Dally, Sr. VP of Research from Nvidia, gave a keynote address and said, “I want high-level tools to help me do design exploration.” Bill explicitly listed power tools for architectural exploration that can provide rapid evaluation of the power and performance impact on architecture tradeoffs. Given the size of the bets being placed, it would certainly seem to make sense.
The new 2009 ITRS report is out (or at least a good portion of it any way). Something new that caught my eye in the report is the chart shown below. Under the “Design” portion, the ITRS shows the evolving role of design phases in overall system power minimization. It shows where the relative power savings are coming from now and how over the next five years the industry needs to shift those efforts more towards the front end where most of the real savings can take place.
The report is also more pessimistic about the power characteristics of future technology nodes, especially if the SoC Consumer Portable Power Trend chart is any indication.
The evidence is mounting and the time-to-market pressures seem to only be getting worse. If you are a designer, even if you aren’t at one of the large processor companies, chances are that on a relative scale the design bets you’re making are at least as important to the financial success of your company. Can you really afford not to look at ways to take every possible advantage at the architectural level?
—Barry Pangrle is a solutions architect for low power design and verification at Mentor Graphics
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