Making Waves In Low-Power Design

Barry Pangrle
In a blog last April we looked at a potential candidate technology that just might be able to produce an economically feasible method for implementing delay insensitive circuits in CMOS. The basic idea behind this technology has been around since at least the 1990s and is better known as Null Convention Logic™ (NCL). Much of the work in this area was pioneered by Karl Fant and Scott Brandt and more information on NCL is available here.

Wave Semiconductor has made available some early results of circuits that they’ve constructed in TSMC’s 28nm HP process and they’re making some pretty impressive claims about 8-bit processors implemented in their Wave Threshold Logic™ (WTL) hitting speeds of over 10GHz and operating from 280mV to 2.2V with zero logical errors.

At the heart, this is a dual-rail asynchronous logic so there is an associated area penalty, but the company claims that it’s in the 30% to 50% range when compared to standard clocked Boolean logic circuits. So what does the additional area buy you? Well, Wave claims that the delay insensitivity means that the design effort becomes much easier as PVT variation is gracefully handled and functional yields should also be higher. The fact that it is non-glitching and self-coordinating means that there is less wasted energy and reduced clock tree complexity. Migrating designs to future technology nodes should also become easier.

I gave a basic description of the logic in the earlier mentioned April 2013 article and there is more information available in this white paper. The basic symbol for a threshold gate is shown below, where m indicates the threshold level (the number of inputs that need to be “1”) to generate a logical “1” at the output.

Figure 1. Threshold Gate Symbol

Every variable has 2-bits representing it, hence the dual-rail logic designation. A logical value “0” is represented by “10” and a logical value “1” by “01”. “00” represents “NULL” or “NOT_DATA” and “11” is not allowed by convention. Wave has constructed a gate library of primitive WTL functions to replace all four-input Boolean expressions that requires only 28 members. One can think of a circuit as starting in a completely NULL state with 0’s throughout the netlist. As values become available an evaluation wave (or data wavefront) spreads across the design. Once the end nodes are DATA, i.e. valid, then a reset wave (or NULL wavefront) can be sent across the circuit to ready the logic for the next evaluation wave.

Pipelines can also be generated with this logic. Figure 2 below shows a simple example of a combinatorial pipeline built using WTL technology that is also described in the white paper. It shows how a data value entered at a1 propagates through each stage of the logic. The blue lines indicate data and the green lines are completion coordination signals. The inverted feedback (coordination) signals are used to generate a NULL cycle at the input of the preceding stage. You will notice that this produces a 3-stage delay line in this degenerately simple case. The black arrows show the propagation of the value at a1 to OUT in 3 cycles. The red circle indicates when the first stage is again ready to accept a new data wave. Of course WTL pipelines can be built to any depth and higher levels of complexity.

Figure 2. Simple Example of a WTL Combinatorial Pipeline

The initial results look quite promising and Wave is aiming to help reduce the NRE costs associated with designs in leading edge technology nodes. The whole topic of whether the ever-escalating NRE costs in the industry are creating a barrier to future innovation will be one of the focal points of an upcoming panel session at this year’s ISSCC. A number of industry luminaries are scheduled to appear on the panel and it’s the first panel session that I can recall seeing that even has its own web site. If you’re an IEEE member, you can attend this panel session for free. Just be sure to bring you membership card.