Power Optimization Considered

The explosive emergence of hand-held computing and entertainment devices fuels an ever-increasing demand for longer battery life. In fact, 70% of all new hardware development is targeted toward mobile devices. Ancillary to this phenomenon, technology scaling has increased the number of transistors that can be packed per unit area. More and more functionality can be put into electronic devices. This also translates into large increases in the amount of power (especially, leakage) consumed by these devices. This dense packing of transistors into small areas also causes issues with power integrity and IR drop, and it can lead to inductive effects.

As a result of these trends, power analysis and optimization have become a primary concern in chip design and verification. But before we look into analysis or optimization, it is imperative that we define the different power metrics: energy, power, and peak power. Energy is the effort required to perform a certain task. Power is defined as the energy required per unit time. Peak power is the maximum power requirement at any point of time.

The question then is which metric to optimize. The answer is application-dependent. You want to address peak power to maintain supply voltage levels, create a robust power-grid design, and increase reliability. You want to work on average power and energy to increase battery lifetime, address heat dissipation and cooling requirements, enhance noise margins, reduce energy costs, and increase reliability.

There are hundreds of techniques used to reduce power from the system to the layout level. The thing to remember is that controlling power pretty much means controlling the supply voltage, leakage current, switching capacitance, or the toggle activity of signals. It is also critical to keep in mind that the majority of a chip’s power is determined very early on in the design cycle. Once you have frozen the architecture, decided on the functional blocks and laid out the state boundaries, the power is pretty much fixed. Therefore, any changes done early on in the design flow will likely have lot more impact on the design power than the ones done later at gate or layout level.

It is essential to understand what aspect of power a particular optimization targets and what the tradeoffs are. Reducing the supply voltage can save power but at the cost of speed. Reducing the clock frequency can reduce power but not energy. Reducing physical capacitance can have an adverse impact on speed. Faster execution does not always mean less energy. Finally, you have to explore making sequential changes to realize maximum power savings.

A lot has been written about the various system-level techniques for reducing power. There are also many commonly used micro-architectural techniques that can be applied either at the system level or the RTL, depending on whether enough information is available to make these changes. Detailing these techniques is beyond the scope of a blog. I do explain these in depth in the webinar “Techniques for Reducing RTL Power at Various Levels (RTL #4)”.

Calypto’s low-power platform can help automatically perform some of these optimizations and help with manual implementation of many of the rest.

Remember, it is important to know which power metric is being targeted to make an informed choice about the optimization technique. There are several system and RTL power optimization techniques that utilize either reduction in voltage, switching capacitance, toggle activity, or frequency to reduce power.

To learn more, please join our high-level synthesis Webinar “HLS 5: Optimizing SystemC/C++ Hardware Architectures through HLS”, Tuesday, Jan. 14 at 10 a.m. PST. You can register for it here. View all our upcoming events and webinars click here.