Return To Claremont

By Barry Pangrle
Intel’s Gregory Ruhl gave an update presentation on Intel’s Claremont IA-32 near-threshold voltage (NTV) and wide dynamic range processor at Hot Chips 24. (I’ve also written an earlier article about Claremont here.) There are many challenges in building a part that operates across a broad range of voltages and Intel listed reduced ratios of on-current vs. off-current, reduced noise margins and the impact of variability resulting in circuit functional failures. The power/performance profile also becomes extremely sensitive to PVT (process, voltage and temperature) variation. The potential for much improved energy efficiency is the lure for going down a path where the tools and methodologies are not yet mature for this type of design.

Claremont is based on Intel’s legacy P54C IA-32 core (circa 1994). It’s a superscalar, in-order pipeline architecture with a pipelined floating-point unit. It incorporates dynamic branch prediction and separate instruction and data caches. Figure 1 below shows the normalized energy per cycle for the design at different operating points. The savings are quite substantial at lower voltages. It should be noted that this design was manufactured using Intel’s 32nm High-K Metal Gate process with one poly layer and 9 layers of metal (Cu). The core is 1.96mm2 and uses 6 million transistors.

Figure 1: ~5x Energy Reduction Achievable (Source: Intel)

To give you a better idea of what the designers are up against, Figure 2 (from a UC Berkeley lecture found here) shows how a typical MOSFET’s drain current is impacted at a given drain-source voltage when the gate-source voltage varies. Clearly the drive strength falls off (exponentially) below the threshold voltage, which also exacerbates any variability issues. (I previously wrote about the impact of body bias impact on threshold voltages here).

Figure 2. ID vs. VGS for a Given VDS

The part was designed to hit three target operating points: 0.5V/66MHz, 0.75V/333MHz and 1.05V/525MHz. In fact, Intel reported the results shown in Figure 3 below where they were actually able to achieve a range of 0.38V/10MHz to 1.1V/741MHz using 1.5mW and 445mW of power respectively.

Figure 3. Power/Performance Characteristics (Source: Intel)

In order to get to this point, Intel reported performing variation-aware library pruning to ensure reliable operation and limited transistor stacks to 3, used no wide transmission gate muxes and no contention circuits. They pruned minimum sized and low drive strength cells, redesigned sequentials with interruptible and upsized keepers, used 10 transistor single-ended transmission gate register file cell topology and still maintained legacy full swing 3.3V I/O support. All in all it’s an impressive effort with promising results and it will be interesting to see where Intel takes this technology going forward.

—Barry Pangrle is an independent power architect in Silicon Valley.