Revolutionizing High-Performance Silicon With Next-Gen Chiplets

By Shivi Arora and Sue Hung Fung

As 5G wireless communications systems continue to be deployed, enterprises are busy planning for 6G—the next generation of wireless communications set to transform our lives. Poised to merge communication and computing, 6G promises to create a hyperconnected world that blends digital and physical experiences with ultra-fast speeds and low latency as a starting point. Building on the foundations laid by 5G, 6G will continue supporting improved data latency, security, reliability, and the ability to process massive volumes of data in real time. It will also challenge what’s possible by bringing new, groundbreaking capabilities to the forefront, including expanded ubiquitous connectivity, integrated sensing and communication, and advanced artificial intelligence.

In today’s technology-driven era, we rely on our handhelds, smartphones, and mobile devices to fulfill day-to-day tasks, most of which are driven by on-device or cloud-based AI and ML. Connectivity and compute power are the most important factors enabling on-cloud large language models (LLMs) to process and respond to human interaction. The communication infrastructure currently operates over 5G networks. It started not long ago with bandwidth in the kilobits per second (Kbps) range in 2G and has now evolved to gigabits per second (Gbps) in 5G. On the horizon, the existing 5G wireless communication infrastructure will soon evolve to 6G, offering bandwidths of terabits per second (Tbps). With the increasing number of devices and complex AI workloads, a much higher network bandwidth is needed. Network infrastructure giants are already looking to update their hardware to support speeds 50-100 times faster than 5G, with air latency under 100 microseconds, and even wider network coverage and reliability.

With this new infrastructure for 6G, carrier support and hardware/software support will require new RF designs and chipsets capable of supporting higher communication frequencies, possibly up to 1 THz. Although newer networks may be designed for more data bits per kilowatt of power efficiency, the increase in density, traffic, and processing speeds tends to negate these savings.

The wireless technology trend of the existing 5G network is built around innovation in processors and wireless technology on mobile devices, and in wireless base stations and cells. Base stations are replaced by RUs (radio units), DUs (distributed units), and CUs (centralized units). The radio units manage antennas in real time through multicore processor chips. The distributed and centralized units provide support for the lower and upper layers of the protocol stack, respectively. These protocol stacks operate on compute chiplets, which are mounted on hardware acceleration cards to handle protocol processing. Radio, distributed, and centralized units need to handle a lot of radio processing and traffic data. With even higher throughput and extremely complex workloads in the new 6G infrastructure, network architecture, software, and hardware accelerator card equipment will need an upgrade or redesign to process and handle much larger amounts of data. The processor compute chiplets on the accelerator cards manage up to dozens of antennas simultaneously and will need to grow in compute power as requirements become more complex with the move to 6G.

To fulfill the needs of this rapidly advancing semiconductor industry, Alphawave Semi is collaborating with Arm on a sophisticated chiplet that uses Arm’s Neoverse Compute Subsystems (CSS). These compute chiplets are vital for supporting the demanding requirements of 6G/5G infrastructure, cloud and edge compute applications and for handling enterprise networking, server, and AI/ML markets. This partnership integrates the silicon-proven IP portfolio from Alphawave with Arm’s Neoverse CSS N3 to handle intensive workload efficiency, performance optimization and power savings in both compute and accelerator chiplets.

The Neoverse ecosystem of hardware and software is targeted for new generations of wireless mobile communications equipment and the wireless infrastructure’s cloud-based deployment. Software developers continue to port operating systems and tools to support Arm’s Neoverse class compute subsystems. These tools allow developers to scale their code using SVE (Scalable Vector Extension) to different vector lengths, reflecting new or updated hardware architecture, whereas traditional processors only handle vectors of specific widths. Traditional architectures require code to be rebuilt to handle additional vector bandwidth updates. SVE allows scalable vector performance on 5G RAN (Radio Access Network), a wireless communication architecture that uses 5G radio frequencies to provide wireless connectivity to devices. RANs perform complex processing when voice and data are converted to digital signals and transmitted as radio waves to RAN transceivers, to the core network, and onto the internet. The radio spectrum requirements for performance, capacity, speed, and latency will be redefined to support 6G, along with the connections of millions of devices per square kilometer. Base stations, antenna units, edge data servers, and cells will need to migrate to support an upgraded network architecture.

Arm’s Neoverse platform is delivering technology for building seamless networks as wireless technology continues to move to next-generation core designs. The Neoverse platform offers high performance per watt efficiency over traditional processors in clouds and 5G networks. The Arm CMN-700 integrates the Arm Neoverse CPU Cluster, high-speed L1/L2/L3 cache, DDR/LPDDR memory, and high-speed I/O, along with other management IP elements through an on-chip interconnect. It uses Memory Partitioning and Monitoring (MPAM) to share system-level resources like cache and DRAM memory bandwidth. CMN-700 supports CCIX, CXL, and CHI-C2C protocols for multi-die use cases and provides a low-latency path to DDR and CXL-attached memory pools.

By utilizing a high-performance process node, Alphawave Semi, working with Arm and its technologies, can offer compute chiplets that enable faster development, low risk and reduced time-to-market by packaging known good dice with customers’ accelerator chiplets. This collaboration is part of Arm’s Total Design initiative, which aims to create an ecosystem that speeds up the development of specialized silicon solutions based on Neoverse CSS. This ecosystem-centric approach simplifies the design and development of complex computing solutions and addresses the increasingly sophisticated demands of modern digital infrastructures and wireless networks.

The compute chiplet leverages standard packaging as a modular chiplet and can optionally be implemented as a monolithic ASIC. The chiplet portfolio is complemented by a connectivity suite of standards-based, silicon-proven technologies, including PCIe, CXL, Universal Chiplet Express (UCIe), and memory subsystems. Alphawave Semi’s compute chiplet is built using Neoverse CSS N3, which is based on Arm’s Neoverse N3 CPU and the CMN S3 Coherent Mesh Network to create a compute SiP that excels in scalability, modularity, and power efficiency.

Alphawave Semi’s unique chiplet-based design platform includes a variety of chiplets: an Arm-based Neoverse class compute chiplet, a multi-protocol I/O chiplet, and memory chiplets for various application spaces. The compute chiplet is the latest inclusion that expands the chiplet portfolio capabilities by adding more modularity and functionality for memory and I/O components to be attached to this chiplet. This compute chiplet addition provides yet another chiplet option to customers who wish to enhance the overall performance of their SiP by choosing from a variety of off-the-shelf chiplet products from Alphawave Semi’s portfolio. This broad suite of technologies allows for the flexible development of custom-tailored system-in-package (SiP) solutions that meet specific customer requirements with different criteria for advanced packaging choices, IP connectivity, or data bandwidth performance.

Alphawave Semi’s partnership with Arm represents a significant stride in enabling greater performance in new innovative technologies, such as wireless network platforms. This long-term vision will provide greater performance for the complex compute requirements needed by advancements in modern 6G/5G network infrastructure as well as cloud and edge-based applications. This unique collaboration highlights Alphawave Semi’s role in the development of high-speed, energy-efficient computing platforms.

Sue Hung Fung is principal product marketing manager at Alphawave Semi.