Between A Rock And A Hard Place

By David Abercrombie
My previous articles included a lot of discussion about correcting error violations in double patterning (DP). This time let’s take a step back up the design flow. DP requires a design team to make some important decisions about standard cell design methodologies, or risk running into serious placement issues down the line. Understanding why this is so, and what your options are, will not only help you make the best choices for your company, but also enable you to keep your DP designs moving smoothly through your design flow.

For the most part, cell libraries designed for processes that don’t require double patterning layers are placement-independent. This independence allows the cells to be very compact, while providing maximum flexibility for the place and route (P&R) tools to minimize area utilization. With the need for double patterning layers at advanced nodes, this placement independence of very compact cells no longer can be taken for granted, even when each cell is DP-clean. Figure 1 provides a simple example of how a double-patterning error can occur on a single interconnect layer with two different DP-clean standard cells.

Figure 1: Two DP-clean cells can form an odd cycle violation when placed adjacent to each other.
Each cell contains a VDD strap across the top and a VSS strap across the bottom. The arrows represent spacing between shapes that require color alternation. Each cell by itself has no DP violations, as there are no odd cycles within each separate cell. However, when the cells are placed adjacent to each other, the spacing interaction between a polygon in each cell forms an odd cycle crossing the cell boundary. Because of this DP restriction, these two cells cannot be placed directly next to each other, limiting the flexibility of the P&R tools.

One potential solution to this problem is shown in Figure 2. The original two cells (Cell A, Cell B) were modified (Cell A’, Cell B’) to add extra space to the left and right borders of each cell. This space avoids the creation of the odd cycle when these cells are placed next to each other, but it also makes the cells wider, increasing the design area.

Figure 2: Modifying the width of the cells avoids odd cycle violations in abutting placements.

However, adding this extra space on the left and right borders of the cells still does not guarantee placement independence in DP design. Figure 3 shows the modified Cell A’ from Figure 2 placed next to a new Cell C. Both of these cells have extra space on the left and right borders, so there is no spacing arrow between the nearest neighbor polygons at the placement abutment. However, an odd cycle that traverses through the power and ground rails has been formed across these two cells. Because the interior polygons interact at minimum spacing with the power and ground polygons, odd cycles like this can occur.

Figure 3: Odd cycles formed between cells through the power and ground rails.

Figure 4 demonstrates the simplest solution to this new issue. By adding additional height to the cells (so that the interior polygons have more than minimum spacing to the power and ground rails), these odd cycles can be eliminated.

Figure 4: Cells with height and width modifications to avoid odd cycle violations in abutting placements.

Of course, the downside of using these two solutions is that we’ve now added area in both the vertical and horizontal direction. So, a tradeoff has been made between increasing the area of the cells in the library and the placement freedom of the P&R tools.

An alternate approach to solving these DP-aware placement issues with anchoring is shown in Figure 5. In this example, we use color anchors to force specific color assignment to the polygons on the outer border of the cells. The color selection has been chosen so that any cell can be placed next to any other cell without causing a same color spacing error. This allows us to design the cells with minimum vertical and horizontal area, but still have them be placement independent.

Figure 5: Border color anchoring technique for assuring placement independence.

However, implementing this approach can be a complex process, with multiple limitations that must be carefully managed:

1. Forcing boundary polygons to a particular color introduces spacing restrictions within the cell. For instance, on the left border of Cell A, the two small polygons and the power rail are assigned to the blue color. Because all of the polygons on this edge and the power rail must be constrained to the same color, they cannot be at minimum space between each other without causing a same color space violation.
2. Anchor path violations can potentially occur between the anchored polygons on one edge of the cell and the anchored polygons on the other side of the cell. This again limits the flexibility of the interior design of the cell. These limitations can potentially lead to larger area cells, negating the value of this approach.
3. The forced anchoring of one color to the left side and the other to the right side prevents the P&R tool from flipping cells, limiting some of the tool’s placement flexibility.
4. Finally, given all these conditions, a practical automated means of guiding designers through the implementation of such a strategy is extremely difficult. Realistically, designers are forced to manually set the appropriate anchors and hope that they did it correctly.

There is one more option (with two variations) that enforces a “framing” methodology, similar to the anchor technique. Figure 6 demonstrates the first variation of this approach to guiding cell design. A temporary “frame” of anchored polygons is placed around the borders of the cell. Because of their spacing to the cell borders, these polygons enforce a particular coloring onto the cell polygons at the edges. These anchored polygons are only temporary, and are removed once the cell design is complete. If automated color coloring is applied to this cell, these frame anchors force the cell polygons to be colored similar to the border coloring methodology shown previously.

Figure 6: Use a temporary frame of anchor polygons to force a particular coloring of the IP before placing in the full chip.

A more flexible approach is the second variation, which uses a colorless temporary frame when designing a cell (Figure 7). DP odd cycle checks run against a cell design with this type of frame layout ensure that the VDD polygon is the opposite color to the VSS polygon, and that all left border polygons are the opposite color of the right border polygons, without actually anchoring any of them to a particular color. This approach allows us to leave the cells in an uncolored state, but still guarantee placement independence.

Figure 7: Use a frame of colorless polygons if you plan to leave the IP colorless in the full chip.

In the end, there are many options to placement-friendly DP-aware standard cell design. All of them involve potential trade-offs between complexity of design, cell area, placement independence, and ultimately die size and time-to-market. While the technique you choose to use will be determined by your organization’s structure and processes, as well as your own experience with and knowledge of DP design, the one thing you can’t afford to do is wait until layout to consider these DP issues. If you do, you will surely be caught between a rock and a hard place, and your design schedules will feel the pain. Work through these issues early (before your design teams start doing layout), and enforce an intentional methodology that meets your particular business goals. You’ll find yourself in a much more comfortable position, I promise.

In my next article, we’ll look at how DP affects the routing methodologies.

—David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics.