Is it possible to manage power in SoC designs simply?
When it comes to chip design we speak constantly about managing complexity – how best to architect for it, how to manage it, what design techniques to use, what the impact on the system will be etc. – but we don’t speak too much about making the design more simple. Instead, we heap on more complexity to manage the complexity.
As with everything else in life it seems just because something is simple doesn’t mean it is easier.
Case in point. Almost three years ago, my husband and I along with our two kids, two basset hounds and one cat packed up and headed east out of Silicon Valley in search of a simpler life. We had fallen in love with a 150+ year old farmhouse in Southern Indiana and dreamt of the simple life we’d have and our kids would know. Yes, we had room to roam on our property, we grew many of our own veggies, we had a wood stove as our main heat source, we kept chickens for the eggs — all the while we worked on what I thought was our dream home. And it was a lot of work! A simpler life for sure but much, much more work every day.
I wonder how this correlates to power management. Is it possible to architect a simple and elegant design in a timely manner that manages power efficiently or would that task prove too cumbersome?
Please do let me know your thoughts and experiences on this!
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