Week in Review: IoT, Security, Auto

By Jeff Dorsch - 10 May, 2019 - Comments: 0

Internet of Things Microsoft this week introduced IoT Plug and Play, a no-code toolkit for connecting Internet of Things devices to the cloud. The company touts it as a new modeling language to pump up the capabilities of IoT devices through the Microsoft Azure cloud service. The Azure IoT Device Catalog lists devices that support IoT Plug and Play, such as the STMicroelectronics SensorTile.bo... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 26 Oct, 2018 - Comments: 0

Internet of Things Arm aims to accelerate Linux-based embedded design through providing quick access to the Cortex-A5 CPU under the Arm DesignStart program. Developers can work on embedded and Internet of Things system-on-a-chip devices for gateways, medical systems, smart homes, and wearable electronics. IP access to the Cortex-A5 is now $75,000, with one-year of design support from Arm exper... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 14 Sep, 2018 - Comments: 0

Internet of Things NXP Semiconductors provided its A71CH trust anchor to Google IoT Cloud, enabling authentication for Google IoT Cloud Core. The technology helps to secure edge devices for Internet of Things deployments. Separately, NXP announced the promotion of Kurt Sievers, executive vice president and general manager of the chip company’s automotive business, to president of NXP Semicon... » read more

Week in Review: IoT, Security, Auto

By Jeff Dorsch - 24 Aug, 2018 - Comments: 0

Internet of Things Arm uncorked its first forward-looking CPU roadmap and performance numbers for client computing. The company said it expects to deliver annual performance improvements of more than 15% per year through 2020. The targeted market includes 5G, always-on, always-connected devices. C3 IoT will work with Google Cloud to support artificial intelligence and Internet of Things dep... » read more

Knowledge Centers
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Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Calsonic Kansei

Week in Review: IoT, Security, Auto

Week in Review: IoT, Security, Auto

Week in Review: IoT, Security, Auto

Week in Review: IoT, Security, Auto

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