tag: capacitive coupling

Using Virtual Metal Fill To Predict The Impact Of High Level Nets
By Vamsi Thatha - 14 Sep, 2023 - Comments: 0

A recent blog post discussed the use of virtual metal fill (VMF) to predict the effects of real metal fill when performing RC extraction on a chip layout. This enables static timing analysis (STA) closely correlated with final post-fill results without incurring the time to perform the actual metal fill insertion during the layout-STA loop. VMF is fast enough to be run in every iteration of thi... » read more

Using Virtual Metal Fill To Solve Real Design Problems
By Vamsi Thatha - 08 Jun, 2023 - Comments: 0

People learning about semiconductor manufacturing might well be confused by the concept of metal fill. It seems perfectly intuitive that laying out a complex chip will result in some regions with fewer transistors and metal interconnect than others. It makes sense that there will be areas that are mostly empty. So why spend money on more complicated masks and on extra metal just to fill those e... » read more

Symptoms Of SoC Electromagnetic (EM) Crosstalk
By Anand Raman - 14 Feb, 2018 - Comments: 0

By Anand Raman and Magdy Abadir Have you ever had your silicon demonstrate unexpected behavior? Have you ever found unexplainable design failure or performance degradation? A number of issues could be the culprit - from overloaded signal nets, a noisy power grid, or increasing temperature - but one problem often overlooked is electromagnetic (EM) crosstalk. Electromagnetic (EM) crosstal... » read more

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