Week In Review: Design, Low Power

By Jesse Allen - 15 Apr, 2022 - Comments: 0

Ansys will acquire cloud simulation provider OnScale. OnScale's technology will be used to provide a cloud-native, web-based UI for device-independent access to Ansys’ simulation technologies as well as creation of simulation-based vertical applications. “OnScale’s cloud-native technology combines the limitless compute power of cloud supercomputers with an intuitive web-based front end, m... » read more

Week In Review: Design, Low Power

By Jesse Allen - 08 Oct, 2021 - Comments: 0

Arteris IP plans to become a public company. It filed a registration statement with the SEC for an IPO, and intends to list on Nasdaq. The number of shares to be offered and the price range for the proposed offering have not yet been determined. Arteris IP provides network-on-chip interconnect IP, cache coherent interconnects, and packages to speed functional safety certification alongside IP d... » read more

Week In Review: Design, Low Power

By Jesse Allen - 19 Feb, 2021 - Comments: 0

Analog Devices acquired the wireless assets of Comcores. Analog Devices plans to continue to evolve the wireless technology and participate in the O-RAN forum. Teams based in Denmark and Poland, including Comcores founder and former CEO, Thomas Noergaard, will join ADI. Comcores will retain its other lines of intellectual property and digital systems business, Chip-to-Chip and Ethernet Systems ... » read more

The Week In Review: Design

By Jesse Allen - 17 Mar, 2017 - Comments: 0

Business Andes Technology went public this week on the Taiwan Stock Exchange with an initial stock listing of 40,611,915 shares at a price of NT$65.10 (USD $2.12) per share. The shares began trading March 14, 2017, under the TWSE ticker symbol “6533.TWO.” Andes plans to use the proceeds to expand the company's R&D effort, to fuel international expansion into the U.S. and Europe and t... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Comcores

Week In Review: Design, Low Power

Week In Review: Design, Low Power

Week In Review: Design, Low Power

The Week In Review: Design