Do Parallel Tools Make Sense?

By Brian Bailey - 10 Aug, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about parallelization efforts within EDA with Andrea Casotto, chief scientist for Altair; Adam Sherer, product management group director in the System & Verification Group of Cadence; Harry Foster, chief scientist for Mentor, a Siemens Business; Vladislav Palfy, global manager for applications engineering at OneSpin; Vigyan Singhal, chief Oski for ... » read more

Verification As A Flow (Part 2)

By Brian Bailey - 11 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

A Formally Free Lunch

By Brian Bailey - 05 Nov, 2014 - Comments: 0

I am sure many of you can remember the successful events staged by [getperson id="11679" p_name="Eric Hennenhofer"], founder and CEO of [getentity id="22813" comment="Obsidian Software"]. While neither his name nor that of his company may be on the tip of your tongue, DVClub might ring a few more bells. He started it so that he could have a place to meet fellow engineers while enjoying a free l... » read more

Do Students Need More Formal Education?

By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

Cracking The Tough Nut Using Formal Methods

By Brian Bailey - 21 Nov, 2013 - Comments: 1

Pranav Ashar, CTO of Real Intent, assured a packed room of researchers and practitioners of formal methods at the recent FMCAD conference: “Static verification is being used in the verification of designs. Every major chip out there is using static methods for sign-off today.” He used an analogy of cracking a nut. “There’s a right way and a wrong way and if you don’t pick the right me... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: Oski

Do Parallel Tools Make Sense?

Verification As A Flow (Part 2)

A Formally Free Lunch

Do Students Need More Formal Education?

Cracking The Tough Nut Using Formal Methods