Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Susan Rambo UMC and Intel will collaborate on the development of a 12nm semiconductor process platform to address high-growth markets, such as mobile, communications infrastructure, and networking. Apple reportedly pushed back the launch date of its long-awaited electric vehicle and scaled back the self-driving features to L2 driver assistance, according ... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Synopsys will acquire Ansys for about $35 billion in cash and stock. The deal will boost Synopsys' multi-physics simulation capabilities, which are essential for complex 3D-IC designs, where thermal density can have significant repercussions. The acquisition is expected to be finalized in the first half of 2025. Worldwide semiconductor revenue ... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Chip Industry Week In Review


By Jesse Allen, Karen Heyman, and Liz Allan Japan's Rapidus and the University of Tokyo are teaming up with France's Leti to meet its previously announced mass production goal of 2nm chips by 2027, and chips in the 1nm range in the 2030s. Rapidus was formed in 2022 with the support of eight Japanese companies — Sony, Kioxia, Denso, NEC, NTT, SoftBank, Toyota, and Mitsubishi's banking arm, ... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Bosch, Infineon, and NXP were cleared in Germany to each acquire 10% of the European Semiconductor Manufacturing Co. (ESMC), established by TSMC, solidifying the supply chain against future shortages, particularly for automotive chips. “ESMC intends to build and operate another large semiconductor factory in Dresden, in which the three Europ... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, Jesse Allen, and Liz Allan President Biden issued an executive order on the “Safe, Secure, and Trustworthy Development and Use of Artificial Intelligence.” It says entities need to report large-scale computing clusters and the total computing power available, including “any model that was trained using a quantity of computing power greater than 1,026 inte... » read more

Chip Industry Week In Review


By Susan Rambo, Gregory Haley, and Liz Allan SRC unfurled its Microelectronics and Advanced Packaging (MAPT) industry-wide 3D semiconductor roadmap, addressing such topics as advanced packaging, heterogeneous integration, analog and mixed-signal semiconductors, energy efficiency, security, the related foundational ecosystem, and more. The guidance is the collective effort of 300 individuals ... » read more

Chip Industry Week In Review


By Liz Allan, Jesse Allen, and Karen Heyman. Canon uncorked a nanoimprint lithography system, which the company said will be useful down to about the 5nm node. Unlike traditional lithography equipment, which projects a pattern onto a resist, nanoimprint directly transfers images onto substrates using a master stamp patterned by an e-beam system. The technology has a number of limitations and... » read more

Chip Industry Week In Review


By Jesse Allen, Liz Allan, and Gregory Haley A potential government shutdown beginning in November would be "massively disruptive" for the Commerce Department as it continues to disburse critical funding featured in the CHIPS Act to boost semiconductor research and development in the U.S., according to Secretary Gina Raimondo. Global semiconductor industry sales totaled $44 billion in Aug... » read more

Chip Industry Week In Review


By Susan Rambo, Liz Allan, and Gregory Haley. TSMC rolled out the second version of its 3Dblox, which creates an infrastructure for stacking chiplets and other necessary components in a package, along with a standardized way of achieving that. Two novel features are chiplet mirroring for design reuse, and what is basically sandbox for power and thermal analysis of different design elements. ... » read more

← Older posts Newer posts →