Utilizing the features that are already built into chips will require advances in software. We aren’t there yet.
By Bhanu Kapoor
Getting power management features already built into chips to be fully utilized is indeed the bigger problem. The features here refer to hooks provided by power management techniques such as voltage and frequency scaling, power gating, and threshold voltage scaling.
There is no doubt that these features have helped a lot in optimizing power consumption. But they are mainly applied at the application level. Each application has a power setting and these settings only scale with applications.
Just as particular settings for an application are a lot more efficient than the same global settings for all the applications, changes in settings during an application can bring in the next level of power efficiency. However, figuring out more optimal execution of an application will require reasonably accurate software power estimation. This is where the problems start and this is where we have stalled.
A good solution to the software power estimation problem requires solutions to some difficult problems: data dependency of power consumption, accurate power modeling of the underlying hardware, and expertise in parallel software development.
It turns out that the power management features can only be efficiently utilized in the context of parallel execution of software (assuming multi-core SoC) and we are still dealing with the issue of good tools for parallel software development. As we solve the parallel software development puzzle and add power optimization parameters to the mix, we start to see why it is difficult to utilize the power management features in place today.
—Bhanu Kapoor is the president of Mimasic, a low-power consultancy.
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