The Good Kind Of Bias

By Barry Pangrle
Back gating, body bias, substrate bias, and back bias all refer to a technique for dynamically adjusting the threshold voltage of a CMOS transistor. CMOS transistors are often thought of as three-terminal devices with terminals for the source, gate and drain. It’s quite common, though, to have a fourth terminal available connected to the substrate (or body).

Most engineers understand the substrate bias (with respect to the source) can be used to vary the threshold voltage of a CMOS transistor, which in turn impacts the leakage current and performance of the transistor. Push the bias one way and the threshold voltage drops, increasing the switching speed and the leakage current. Push the bias the other way and the threshold voltage increases, decreasing the performance and the leakage current. It’s basically another knob to tradeoff performance and power.

This has been a useful technique for designers to help control leakage current. It also can be used to enhance yields. If a chip is fast but runs too hot, it’s possible that substrate bias can be used to slow it down and bring the power back into spec. The formulae for the calculations to determine how much bias voltage is needed and in which direction are readily available and I don’t intend to derive them here. What I am hoping to do in the rest of this article is to provide a brief overview of the concepts behind the technique so that the next time someone asks you, “How does that back bias stuff work,” you can wave your hands a bit and say something that sounds insightful.

For simplicity, I’ll use an NMOS transistor as an example. [Quick review, an NMOS transistor has an n-type source and drain with a p-type substrate.] Oftentimes the p-type substrate is electrically connected to ground for an NMOS transistor. Essentially, the p-n junction between the substrate and the source forms a diode and it is best if that diode doesn’t become forward biased turning it on. Typically, that would be “bad” as current would suddenly flow from the source into the substrate. For our typical NMOS transistor, that would happen if the voltage (from the substrate or body to the source, Vbs) were to rise above about 0.6V. With issues like noise and ground bounce and you’ll want to leave a comfortable margin too.

So our first observation is that we’re pretty quickly limited as to how far we can positively bias the substrate. What about the other direction? Well, providing more negative bias to the substrate just increases the reverse bias of the p-n junction between the substrate and the source. Note that we use the source (instead of the drain) here because CMOS transistors are symmetrical and for an NMOS transistor the source is the terminal that is at the lower voltage. In an NMOS transistor, when it is turned on, the channel is n-type (or negative carriers) so the source is the “source” of electrons that flow toward the more positively biased terminal (the drain).

Our second observation is that we have more room to reverse bias the substrate since this only reduces the leakage current between the source and the substrate by further reverse biasing the junction.

Okay, so which way increases the threshold voltage? Good question. In order to answer this we need to know a little bit about how our NMOS transistor actually turns on. For our transistor to turn on, we must induce a conducting (n-type) channel between the source and the drain so that electrons can flow between them. This is defined to happen at the onset of strong inversion where the charge in the channel effectively makes the channel as strongly n-type as the substrate is doped p-type. In other words, we must attract enough electrons to the channel to sufficiently offset the p-type characteristics of the substrate.

What’s a good way to attract electrons? How about applying a positive potential? Again, for simplicity, we’re going to think of the gate-oxide-substrate part of the transistor between the source and drain as a capacitor. So, if I apply a positive potential (voltage) to the gate (with respect to the source), then I will start to collect negative charge under the oxide in the substrate. I’m on my way now to creating a channel and eventually as I increase the voltage on the gate I’ll have enough charge in the channel to reach strong inversion and the transistor turns on. At this point the voltage level on the gate has reached the threshold voltage. The higher the threshold voltage, the longer it takes for the transistor to turn on (i.e. it’s slower) but it’s also more strongly off when it’s off (i.e. lower leakage). In order to reach the threshold voltage and strong inversion, we have to build up enough charge to overcome the p-type doping of the substrate plus depletion charge plus interface charge plus differences in the work functions.

For our basic model, then, we’ll consider four components that make up the potential needed to reach the threshold voltage: 1) the difference between the work functions for the gate and the substrate, 2) the interface charge (divided by the capacitance across the oxide), 3) the depletion region charge (divided by the capacitance across the oxide) and 4) the surface potential (determined by the amount of p-type doping). The good news here is that we’re going to ignore all except for the depletion region charge. Why? Because the depletion region charge is the component that the body bias acts most directly upon. Similar to the effect of more strongly reverse biasing a p-n junction causes the depletion region to grow, providing a more negative substrate bias causes the depletion region along the channel to also become wider which means I now have more negative charge in the substrate which must be compensated by placing even more positive charge on the gate (i.e. increasing the threshold voltage) in order to form a conduction channel.

So, the simple answer is that placing a negative bias on the substrate for an NMOS transistor effectively increases the negative charge stored in the depletion region along the channel. This charge must then be overcome by more positive charge on the gate thus increasing the voltage on the gate (i.e. increasing the threshold voltage) in order to turn the transistor on. For a PMOS transistor, placing a more positive bias on the substrate (remember n-wells are typically tied high) will require a more negative voltage on the gate to turn it on for the same reasons.

No equations, no band-gap diagrams but hopefully some insight, albeit simplified, of how this technique works.

Jan Rabaey mentions in his book, “Low Power Design Essentials” that the trend is towards increased doping concentrations in the channel which reduces the impact of body bias on the onset of strong inversion or in other words, body biasing seems to have a lesser impact at smaller technology nodes. For readers that are interested in more on the subject, I also recommend Ben Streetman and Sanjay Banerjee’s book, “Solid State Electronic Devices.”

–-Barry Pangrle is a solutions architect for low-power design and verification at Mentor Graphics