The Power Of Logic

By Barry Pangrle
CMOS logic has been dominant since nMOS gave way back in the 1980s. Dynamic logic, like domino, has seen its application in high-speed and often hand-crafted datapath circuits. The potential energy efficiency of operating at near-threshold voltage is very enticing but having to deal with variability issues has made engineers reluctant to try to do more at lower voltages. The question then is, what if there was a way to design logic using today’s process technologies that was more robust with regards to variability?

The Holy Grail has been to develop an economically feasible method for implementing delay-insensitive circuits. Delay insensitive circuits are completely free of delay issues for all of the components in the circuit including the wires and gates. One potential candidate that has been around since at least the 1990s is Null Convention Logic (NCL). Much of this work was pioneered by Karl Fant and Scott Brandt and more information is available here.

To give you a short overview, one of the key concepts is to have a way to recognize when a result is valid. If the circuit is to be delay insensitive, it must be able to tolerate delays and “know” when a result is ready to be used. This is where the concept of “NULL” values comes in. The circuit is initialized with NULL values, and if the input to any gate is NULL, the output also will be NULL.

NULL is essentially a non-data value. Once valid data is presented to the input, valid data can be generated at the output. In this way, it’s possible to conceive of waves of valid data propagating across the circuit and then before the next set of data is evaluated a NULL wave is propagated across the circuit. This forms a cycle of data and NULL propagations. In order to have a solution that is purely delay insensitive and symbolically complete, it is necessary to add a fourth intermediate value (so we have: T, F, NULL, Intermediate}, but we’re not going to go into that here.

A way to avoid adding the fourth value is to add a feedback path to our gates that holds the last valid data until all of the inputs return to NULL. Table 1 shows the truth table for the feedback gate and Figure 1 shows a simple diagram.

The feedback solution, unlike the four-value implementation, is not truly fully delay insensitive. There is what is considered to be a non-critical time relationship between the individual feedback paths and the complete circuit, where the feedback path must stabilize faster than successive wavefronts propagate through the whole circuit. In general, this is relatively easy to achieve.

Figure 2, below, shows an implementation of the feedback gate using a threshold circuit. The threshold circuit maintains the property that it will only propagate a valid data value once enough inputs have received valid data values to cross the threshold. The number inside the symbol represents the threshold level of the number of valid inputs that must be received in order to generate a valid output.

Figure 3 shows the implementation of an XOR gate using our new threshold feedback gates. Note that each variable is represented by two separate lines, but unlike dual-rail logic, A_0 and A_1 are not *always* inverted. While it is true that being active is mutually exclusive, in the NULL reset mode, both A_0 and A_1 will have the value of “0”.

From a power standpoint, the reduction of the need for routing a synchronizing clock signal is an advantage, and the delay-insensitive nature of the circuitry raises some interesting possibilities for reliably running and yielding devices that could work at more energy-efficient voltage points. It would be interesting to see results for an actual silicon implementation using this logic to gauge what kind of a future such a logic may hold.

—Barry Pangrle is a senior power methodology Engineer at NVIDIA. The views expressed in this article are his own and not necessarily those of NVIDIA.