The Power Of Visualization

In the 1990s, the National Semiconductor Israeli site in Herzliya was responsible for the design and verification of the company’s flagship RISC processor.

That was the place and the time when the concept of constraint-random, abstract, coverage-driven verification was born. Engineers realized that without a random generation of stimuli opcodes, it would be very hard to fully verify new processors. Later on, some of these CAD and verification engineers started Verisity and the rest is history.

I did not know it back then but joining this team, fresh from faculty, affected my professional life in many ways. One of my first tasks as a junior verification engineer was to verify a block written by A, a senior designer who was known as someone who has no bugs.

I was told again and again, in the corridor or around the coffee machine, that everyone else was creating bugs. But not A. The guy was a super designer. He had no bugs.

Being the annoying kind of verification engineer I am, I could not accept it and decided this was not possible, so I would ambush A and be there when he tripped. I thought, he must make a mistake at some point. Time after time I would go to A’s desk showing him what I thought was a bug, and time after time he proved me wrong. And for the record, A seemed to be totally unaware of his bugless reputation.

So one day I decided to change my strategy. I came to A’s desk and said casually: “Hey, how come you never have bugs?” He took a rolled paper out of his desk and spread a 1-by-2 meter white paper filled with design block diagram, state-machines, and signals waveforms, drawn neatly by hand.

“While others code using an editor, I draw everything on this paper,” he said. “When I’m able to see the circuit, why would I make mistakes?”

Years later, when I started Vtool and the team started to draw our new debugger, Cogita ideas, it was clear to me we need to utilize the great inherent human capacity of analyzing and processing visual data.

Some 50% of our brain’s computing power is dedicated to visual processing. Many times we are not even aware of it. If you want to catch a ball passed to you during a game, you have two options:

1. To solve a set of complex differential equations.
2. To let your “visual processor” take over and control your actions.

Most people I know chose the second. And it’s the same when you analyze a complex failing simulation scenario — only in this case, you will need a visualization tool to draw the pictures for you.

Here is a short experiment we’ve conducted in the company:

Look at the text below for 5 seconds and tell me what you see.

What is the pattern in this text? You have 5 seconds.

Anything? Okay, now look at this one:

All we did was replace the letter “V” with a blue square.

Visualization is power. As verification engineers, we need to leverage it.

Happy bug hunting.