The Week In Review: Design

M&A

Consultancy Sondrel acquired IMGworks, formerly the design services unit of Imagination. Sondrel says it plans to focus on design services for ADAS systems, AI, and machine vision and learning devices. Terms of the deal were not disclosed.

Tools

Cadence expanded its formal verification platform, JasperGold, adding linting and clock domain crossing apps that address RTL signoff requirements. The Superlint App automatically generates IEEE standard SystemVerilog Assertion (SVA) properties based on RTL as well as performing a comprehensive range of static lint checks on the RTL code, while the CDC app automatically infers CDC intent from the design and comprehensively analyzes structural, functional, and reconvergence issues.

Verific added to its UPF Parser/Analyzer with UPF Elaborator, which applies the power-intent model to the original HDL, creating a power-aware netlist with new instantiations of power-related cells, as well as any required supply network and corresponding control path logic. UPF concepts elaborated in an HDL design include logic and supply ports and nets, power switches, retention, isolation, level-shifter and repeater cells.

In the latest update to Ansys’ simulation suite, the company added a new characteristic mode analysis solver that predicts the fundamental resonance characteristics of an antenna to aid in determining antenna placement and antenna synthesis for devices such as a smart watch, mobile phones and IoT devices.

IP

Rambus, PLDA, and Avery Design launched a silicon-proven PCIe 4.0 sub-system. The sub-system includes a Rambus SerDes PHY, a PLDA PCIe controller and Avery Design’s verification IP. The solution is pre-verified and validated for simple integration into ASICs and is backward compatible with PCIe 3.0 and 2.0.

Deals

ARM will team up with the Center for Sensorimotor Neural Engineering to develop a ‘brain-implantable’ SoC for bi-directional brain-computer interfaces. The project aims to tackle neurodegenerative disorders by decoding the complex signals formed within the brain and digitizing them so they can be processed and acted upon, with the end result of controlling the body’s muscle functions. The SoC will incorporate the Cortex-M0 processor.

Acacia Communications deployed Synopsys’ VCS Fine-Grained Parallelism technology to verify high-speed optical networking and interconnect products, citing a regression turnaround time reduction from 20 hours to under 12 hours.

Cadence and MathWorks integrated the Cadence Virtuoso Analog Design Environment with MATLAB to accelerate processing of large data sets when verifying custom, RF and mixed-signal designs. Designers can use existing MATLAB scripts and share data between the Virtuoso and MATLAB platforms, allowing data analysis to be performed in either tool or split between the two.

ASIX Electronics adopted Synopsys’ USB Type-C Subsystem Verification Solution for USB, USB Power Delivery and DisplayPort.

Numbers

Synopsys released second quarter financial results with revenue of $680.1 million, up 12.4% from the same quarter last year. On a GAAP basis, earnings per share for Q2 2017 stood at $0.34, down 24.4% from $0.45 per share in Q2 2016. Non-GAAP earnings were $0.88 per share for the quarter, up 8.6% from $0.81. The company raised revenue targets for 2017 to $2.65 to $2.67 billion.