Tough Road Ahead For Small IP Vendors

By Bhanu Kapoor
The IP business is a difficult one. The vendors who typically supply to larger semiconductor companies face thin margins and different IP requirements to be supported across their customer base. On top of that, no one wants an IP that has not been proven in the field.

But if you are looking to be an IP supplier for a low-power SoC that will be manufactured in leading edge process technology, it is almost impossible to do that unless you have lots of resources to work closely with your customer base. This limits the choice to a few resourceful IP suppliers. We had a panel on the topic at the DesignCon 2011 with participation from ARM, MIPS, and Synopsys, and I’ll summarize some of the key points here.

Most of the leading power-management techniques use voltage as a handle to reduce dynamic power and leakage power both in active and standby modes. This ties your IP to process technology closely, and you find yourself working with multiple process technology nodes across your customer base. How the SoC will make use of this IP requires you to design power states of the IP that meet your customer needs. This ties you to working closely with part of the SoC team that you are supplying to. Even simple things like how IP is powered up have an impact in overall design because a sudden inrush of current can lead to issues in other parts of the design. How you retain state in various power states and how you isolate your design could be dependent upon customer requirements, too.

One of the issues proposed to the panelists was the fact that it is not clear if an IP provider can effectively provide soft IP along with power specification written in IEEE p1801 format and hand it over to the SoC vendor as soft power-managed IP. ARM Fellow Rob Aitken said that it has indeed been done by ARM, but it took multiple decades of experience, the latest EDA tools, and working closely with the users. For low-power IPs, context may matter a lot. Always-on components are context-dependent, and characterization ranges may depend upon customer needs.

Verification of low-power IPs is a challenge, too. As noted by Kesava Talupuru of MIPS, you need an intelligent mix of simulation, formal, and structural techniques to verify low-power designs. A typical power manager is both hardware and software controlled, and that requires a good knowledge of a system-level power-state dependent usage model of your IP to carry out validation.

Advances are being made on the EDA front that will help with some aspects to qualifying soft IP as pointed out by Prapanna Tiwari of Synopsys. One of the major advances is in the standard itself. The IEEE p1801 standard helps specify the power architecture of your design. The hardware description languages such as Verilog, VHDL, and SystemVerilog did not deal with voltage as a variable. and this was a big gap to be covered for the development of EDA tools. Function simulation is impacted by power behavior and simulation tools such VCS from Synopsys are now power-aware.

Larger IP players such as ARM, MIPS, and Synopsys will have the resources available to work closely with the customers in developing low-power IPs. Nothing in this debate pointed to smaller players being able to do the same. It will be good hear about your experiences with either the development of low-power IP or the usage of a low-power IP in an SoC.

–Bhanu Kapoor is the founder and president of Mimasic, a low-power consultancy.