June 2010 - Page 3 of 3 - Semiconductor Engineering

Corners Up, Margins Down

By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Ed Sperling Complexity, less room for error and concern over adding any extra wires or circuits into chips because it may boost power consumption or affect the thermal profile are making it more difficult to tackle all the corners on an SoC. The problem gets worse with mixed signal chips, where the corners are far less definable. And it gets even more complex when it comes to turning on ... » read more

Changing Opinions About Noise

By Ed Sperling - 10 Jun, 2010 - Comments: 0

By Brian Fuller On a sunny, warm May day in 2009, NIST researcher Jason Campbell took the stage at an IEEE event in Austin with a presentation that was sure cast a pall over the booming low-power semiconductor world. Campbell’s paper, written with Liangchun Yu, Kin Cheung, Jin Qin, John S. Suehle, A. Oates, Kuang Sheng, was entitled “Large Random Telegraph Noise in Sub-Threshold Opera... » read more

Knowing When To Panic

By Bhanu Kapoor - 10 Jun, 2010 - Comments: 0

By Bhanu Kapoor Sometimes we hear that the number of power domains in SoCs have increased significantly and that makes power management verification difficult. True, the numbers have gone up from say 2 or 3 to between 7 and 10, but these are not large numbers by any means and you can write tests to ensure that each of these power domains are covered for power related tests. Power-related tests... » read more

Timing Closure And Denial

By Ron Craig - 10 Jun, 2010 - Comments: 0

By Ron Craig I live in a reasonably remote area—defined as more than 10 miles from the nearest Starbucks. Given that I spend a fair amount of time driving, I’m conscious of things like safety and mileage. One thing that has a big impact on both is the health of my tires, and after having a recent replacement set installed I noticed that my ‘local’ tire shop offered things like regula... » read more

The Road To DAC: One On One With Wally Rhines

By Ed Sperling - 10 Jun, 2010 - Comments: 0

Mentor Graphics' CEO talks with Low-Power Engineering about the cost of designing a chip, the rising percentage of embedded software, the shift to FPGAs and what's changing in EDA. [youtube vid=Zjs9xz4iD3E] » read more

Giant Steps—Backward

By Ann Mutschler - 10 Jun, 2010 - Comments: 0

With DAC headlining next week, power is sure to take center stage given its prominence as a key pain point for design engineers that are always on the lookout for a new technique to ease their power management burdens. In many low-power designs, asynchronous technology may be just the thing. One of the biggest disadvantages of the clockless CPU is that most design tools assume a clocked CPU ... » read more

The Road To DAC: One On One With Lip-Bu Tan

By Ed Sperling - 04 Jun, 2010 - Comments: 0

A look at what's driving Cadence's new EDA 360 strategy, the problem areas in EDA and why the company decided to buy Denali. [youtube vid=zreEWGsCe5A] » read more

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