October 2010 - Page 2 of 3 - Semiconductor Engineering

Experts At The Table: Timing Constraints
By Ed Sperling - 15 Oct, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. Wha... » read more

The Good Kind Of Bias
By Barry Pangrle - 07 Oct, 2010 - Comments: 1

By Barry Pangrle Back gating, body bias, substrate bias, and back bias all refer to a technique for dynamically adjusting the threshold voltage of a CMOS transistor. CMOS transistors are often thought of as three-terminal devices with terminals for the source, gate and drain. It’s quite common, though, to have a fourth terminal available connected to the substrate (or body). Most engineer... » read more

Power Intent Files Drive Low Power Adoption
By Luke Lang - 07 Oct, 2010 - Comments: 0

By Luke Lang “The adoption of EDA tools is actually a very slow process.” This quote by Wally Rhines of Mentor Graphics was highlighted in a red box in the June 2010 issue of EDA Tech Forum. I don’t think most of us would argue with that statement. But there are certainly exceptions to that rule, and low-power design with a power-intent file is one such exception. The concept of a pow... » read more

The Value Of Adaptive Body Biasing
By Bhanu Kapoor - 07 Oct, 2010 - Comments: 0

By Bhanu Kapoor Although the use of power gating techniques is essential to manage standby leakage power, it brings in a host of new design and verification issues. This list of new design and verification issues includes putting together a power switch network, incorporating appropriate isolation and retention, addressing x-propagation, dealing with current spikes, and ensuring retention work... » read more

Redefining Performance In Mobile Devices
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler While mobile product trends can be reliably unpredictable, devices are definitely moving towards supporting more software-based browsers, plug-ins for browsers, and downloaded codecs to go to browsers. This results in coming up with a best guess for performance targets. Throw power tradeoffs into the mix and things really start to get interesting. In terms of defin... » read more

User Perspective: Hardware-Software Co-Design
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ann Steffora Mutschler With software teams today twice as large as hardware teams for any given complex SoC project, there is no doubt it is an ideal time to agree on the best way for these worlds to intersect. And even though the semiconductor industry has been actively discussing hardware-software co-design for at least a decade a mainstream solution has yet to be commercialized. Progr... » read more

Performance Plus Lower Power
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Pallab Chatterjee Power and performance often have been seen as something of a tradeoff. Chipmakers focus on one or the other, or they extract a little improvement in both at each new process node. That way of thinking is changing, though. At the recent Linley processor conference, the central theme for both standalone and embedded processors was that architectures have to optimized for ... » read more

Getting Ready For 15nm
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By David Lammers The trends towards vertical transistors, non-silicon channel materials, and resistive RAMs promise to hold center stage at the 2010 IEEE International Electron Devices Meeting (IEDM), set to begin Dec. 6 in San Francisco, Calif. (www.ieee-iedm.org) Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu, Taiwan) will present a 22/20nm technology platform based on a FinFET arc... » read more

Making Too Much Noise
By Ed Sperling - 07 Oct, 2010 - Comments: 0

By Ed Sperling For the better part of a decade talk about signal integrity in mixed-signal designs has been noticeably absent. That’s about to change. Prior to the adoption of a 130nm process, many semiconductor companies actually went on record saying they were considering abandoning plans to ever put analog and digital on the same chip because the noise on digital would interrupt signal... » read more

Experts At The Table: Timing Constraints
By Ed Sperling - 07 Oct, 2010 - Comments: 0

Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. What follows are ex... » read more

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