October 2010


Experts At The Table: Timing Constraints


By Ed Sperling Low-Power Engineering sat down to discuss timing constraints with ARM Fellow David Flynn; Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys; Michael Carrell, product marketing for front end design at Cadence; Ron Craig, senior marketing manager at Atrenta; and Himanshu Bhatnagar, executive director of VLSI design at Mindspeed Technologies. Wh... » read more

Best Practices For Multicore SoC Test And Debug


By Ann Steffora Mutschler In increasingly complex SoC designs, many of which contain multiple cores and multiple modes, determining best practices for testing and debugging is a moving target. Jason Andrews, architect at Cadence Design Systems, said multicore debug is a huge issue. It isn’t easy to do, and there aren’t many good ways to do it. He suggested one approach is to try to u... » read more

The Growing Need For Concurrent Design


By Ed Sperling The move toward concurrent design is escalating at advanced nodes, driven more by the need to ensure that everything works than previous efforts aimed at efficiency and time-to-market. While the concept has surfaced before in limited doses—engineers and EDA companies have been talking about doing more things simultaneously for the better part of a decade—there are some in... » read more

The Future Of 3D Stacking


By Ed Sperling Despite concerns about the lack of tools, an unstable process, questionable interconnects, thermal overloads and electrostatic discharge, 3D stacking appears to be making headway. At the very least, lots of companies of all sizes are betting heavily that it will succeed. The first wave, which is expected to start showing up late next year, will likely come from a handful of t... » read more

Bridging IP With Verification Standards


By Ann Steffora Mutschler Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT -- IEEE 1685, "Standard for IP-XACT, Standard Structure for Packaging, Integrating and Re-Using IP Within Tool-Flows” – with verification IP. The IP-XACT technical committee has been busy over the past year. Formerly an effor... » read more

Talking Heads


The use of more third-party IP inside SoCs coupled with problems encountered at advanced process nodes is turning up some interesting challenges—and pointing the industry in some interesting directions. It’s a well-known fact that third-party IP isn’t always used as it was intended. Even internally developed IP isn’t always used as prescribed. It’s not unusual for chip developers t... » read more

Why Settle For Good Enough


By Kalar Rajendiran The title of this article is missing a punctuation mark at the end and that is by design. Some readers may read it as a question and some others as a statement, depending on their frame of mind and the particular task they are focused on at that time. This article, although not intended to be a psychoanalysis of how people see and interpret what they see, does highlight how... » read more

Should EDA Remain Coin-Operated?


The EDA business model has seen a lot of discussion. Perpetual, time-based, pay as you go, EDA cards, etc., etc. The implications of the chosen business model can have dramatic effects on the overall health of the company involved. Changing the business model can cause mighty companies to topple and weak companies to seem strong (at least for a while). Current trends, such as cloud computing, p... » read more

ESL’s Effect On What Engineers Assume


By Jon McDonald I’m on a cruise this week. I’m spending some time thinking about things other than work, but from time to time even normal life does have an impact on esoterically engineering concepts. As the cruise has visited a number of different ports my wife and I have made many assumptions—assumptions about what we both want to do in port, assumptions about what will be availabl... » read more

Turn Up The Heat


For the better part of two years talk of 3D stacking has been filled with concerns about thermal issues. If you stack logic on logic or memory on memory or CPU on CPU, the chance of causing a fatal failure in the circuitry was assumed to be very high. It turns out that may not be the case after all. Companies working with early prototypes of 3D stacks say silicon itself may be one of the bes... » read more

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