April 2012


Experts At The Table: Hardware-Software Co-Design


By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

Virtual Prototyping Rocks


By Nithya Ruff Achim Nohl was taking a well-deserved vacation last week and asked me to be his guest blogger. To many of you who are regular readers of Achim’s blog, I am new to Synopsys and joined only a few weeks ago to manage the Virtual Prototyping product. I came from Wind River where I managed Embedded Linux product marketing. Having come from 20+ years of managing software of all kind... » read more

Gap Vs. Gap


By Ed Sperling Among tools vendors it’s been standard practice to listen closely to customers but not deliver everything they ask for—or at least not always on the customers’ timetable. This strategy has worked well enough for both sides in the past, but at 20nm and in stacked die configurations, the level of tension between these two worlds is increasing, and the gaps in the tool cha... » read more

Rethinking Timing Optimization


By Ann Steffora Mutschler As semiconductor manufacturing technology continues its march toward 20nm, SoCs are plagued with advanced interconnect delays, cross capacitance, and process variability, as well as area and power constraints—and the significance of these factors is increasing with each passing node. “With lower nodes we are getting advantage on area, more and more logic is get... » read more

From Cryptic Error Messages To Contradictory Commands


By Ann Steffora Mutschler For the past 30 years, semiconductor designers have increasingly relied on automated CAD tools to complete their projects. Over time, these tools have indeed improved from a functionality perspective, but sometimes usability has not kept up with users’ needs. Depending on which tools and what type of use, some tools are easier to use than others, according to Mik... » read more

Boosting Yield With Layout Awareness


By Ann Steffora Mutschler Yield. Just the word can make many engineers cringe and hide in their cubicles—especially with manufacturing problems and excessive power during test increasing causing failures. But the combination of physical data with diagnostics engines may be the light at the end of the tunnel, allowing for easier pinpointing of defects. There are many reasons why a chip fai... » read more

The Interconnect Game


By Ed Sperling Having a single bus protocol is something most SoC engineers can only dream about. Reality is often a jumble of protocols determined by the IP they use, which can slow down a design’s progress. The problem stems largely from re-use and legacy IP. While it might be convenient to use only on an AXI standard protocol from ARM, most chips are a combination of IP tied to specif... » read more

Server Processor War Heats Up


By Kurt Shuler Yesterday’s announcement that Intel will acquire Cray’s interconnect hardware program, including IP and 74 employees, is the latest salvo in the race to develop commercially viable massively multicore server processors. On the surface, this acquisition seems like another instance of Intel beefing up its board-level interconnect technology, after having already acquired Fu... » read more

A Cloud-Connected World


By Frank Ferro If you're paying attention and/or using a smart phone every day (and perhaps it's safer to assume the latter) the ‘cloud’ is no longer a buzzword. The cloud has become grounded in our daily reality. How’s that for a paradox and a visual? But at a minimum, it has become more like a punch line in every consumer's day—without even thinking about it. Projections show that... » read more

Smarter Design Strategies


By Jon McDonald I had an interesting discussion with a customer recently. They were involved in the architectural specification of a fairly complex piece of silicon. They spent a significant amount of time designing the part to work under worst-case power characteristics and defining the power supply requirements for the device in this worst-case use mode. The conversation started with the ... » read more

← Older posts