June 2012 - Semiconductor Engineering

Monsters, Inc.: How Do I Fix These Double Patterning Errors Anyway?
By David Abercrombie - 29 Jun, 2012 - Comments: 0

By David Abercrombie Just mention double patterning (DP) to designers, and you can see the fear in their eyes. There is real trepidation about what kind of monster DP design debugging will be. In this article, I hope to alleviate some of that trepidation by educating you on manual correction techniques, automated fixing hints, and automated fixing capabilities you can adopt to help you with DP... » read more

Leti Looks at Using Strain with FD-SOI for High-Perf Apps
By Various Writers - 29 Jun, 2012 - Comments: 0

The researchers at Leti working on FD-SOI have extremely deep expertise in it. One of the areas they've looked at is performance boosters. With the interest in FD-SOI rapidly increasing on the heels of the recent ST-GF announcement, their work becomes even more timely. A key Leti team wrote a summary of some recent strain work, which first appeared as part of the Advanced Substra... » read more

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 29 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Experts At The Table: The Future Of SystemC
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ed Sperling System-Level Design moderated a discussion about the future of SystemC with Thomas Alsop, corporate design solution expert at Intel; Ambar Sarkar, chief verification technologist at Paradigm Works; Mike Meredith, vice president of technical marketing at Forte Design Systems; David Black, certified training instructor at Doulos. Here are some of the key outtakes of that discussio... » read more

Experts At The Table: Does 20nm Break System-Level Design?
By Ed Sperling - 28 Jun, 2012 - Comments: 1

By Ann Steffora Mutschler System-Level Design sat down to discuss design at 20nm with Drew Wingard, chief technology officer at Sonics; Kelvin Low, deputy director of product marketing at GlobalFoundries, Frank Schirrmeister, group director of product marketing for system development in the system and software realization group at Cadence; and Mike Gianfagna, vice president of marketing at Atr... » read more

Emulation’s Winding Path To Success
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ed Sperling Emulation was developed for verifying complex ICs when simulation was considered too slow. After more than a decade of very slow growth, however, sales have begun to ramp. There are several reasons for this shift. First, SoCs simply are becoming more complex, and the amount of verification that needs to be done to get a chip out the door can bring simulation to a crawl. Desig... » read more

Leveraging The Past
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler It’s easy to forget that not every design today is targeted at 20nm, given the amount of focus put on the bleeding edge of technology. But in fact a large number of designs utilize the stability and reliability of older manufacturing nodes, as well as lower mask costs, by incorporating new design and verification techniques, with 2.5D designs being a prime example. ... » read more

The Trouble With Models
By Ed Sperling - 28 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Models and modeling concepts seem to be on the tip of every tongue these days. Once the promise of sparking true ESL design, the use of system-level models has settled into something more like enabling software development. There is also talk of leveraging models across the supply chain, but is this really possible yet? The concept of doing this incremental refinem... » read more

IP That Makes IP Work
By Frank Ferro - 28 Jun, 2012 - Comments: 0

By Frank Ferro Just how important are IP subsystems to complex SoC designs? It appears much more than you may have thought just a few months ago. With the emergence of SoCs that now support the cloud computing revolution and every major cloud-connected device, SoC complexity is increasing at a dizzying pace. We commonly now see increasing number of IP cores, cores from multiple sources, di... » read more

Merger In Progress
By Jon McDonald - 28 Jun, 2012 - Comments: 0

By Jon McDonald June's been an interesting month, I was at the Design Automation Conference, DAC, in San Francisco, then a week later, the Freescale Technology Forum, FTF. DAC is generally more of a hardware design conference, while FTF generally is a bit more focused on software and systems. This year I was surprised at the similarities in some of the discussions at both shows. At DAC ther... » read more

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