June 2012 - Page 4 of 6 - Semiconductor Engineering

Experts At The Table: Improving The Efficiency Of Software
By Ed Sperling - 22 Jun, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Design sat down to talk about how to write better software with Jan Rabaey, Donald O. Pederson Distinguished Professor at the University of California at Berkeley; Barry Pangrle, solutions architect for low-power design and verification at Mentor Graphics; Emily Shriver, research scientist at Intel; Alan Gibbons, principal engineer at Synopsys; and Dav... » read more

Atrenta Buys NextOp
By Ed Sperling - 20 Jun, 2012 - Comments: 0

By Ed Sperling Atrenta said today it will acquire NextOp Software, a formal tools startup that was created in 2006 and which came out of stealth mode in 2010. The move is interesting as much from a business perspective—it pits Atrenta against Jasper Design Automation, at least in the narrow assertion synthesis and assertion generation markets—as what it says about the increasing interes... » read more

The Resolution Limit of Hard Drive Manufacturing
By Chris Mack - 20 Jun, 2012 - Comments: 0

In lithography, pushing the limits of resolution is what we do.  These efforts tend to get a lot of press.  After all, the IC technology nodes are named after the smallest nominal dimensions printed with lithography (though the marketing folks who decide whether the next generation will be called the 16-nm or 14-nm node don’t care much about the opinions of lithographers).  And the looming... » read more

GloFo to Fab 28/20nm FD-SOI for ST; ST Tech Open to GF Customers
By Various Writers - 15 Jun, 2012 - Comments: 0

Two big pieces of news have recently been announced by STMicroelectronics: to supplement in-house production at Crolles, the company has tapped GlobalFoundries for high-volume production of 28nm then 20nm FD-SOI mobile devices; ST will open access to its FD-SOI technology to GlobalFoundries’ other customers. The high-volume manufacturing will kick off with ST-Ericsson’s ARM-based 2... » read more

Reducing Circuitry To Reduce Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ann Steffora Mutschler Power is at the top of the list of concerns for design teams today. Consequently, engineers are constantly looking at new techniques and architectural approaches to lower and management the power and energy consumption of their devices. This has resulted in some incredible engineering feats, turning parts of a device on and off as needed, applying different volta... » read more

Power Shift
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling For the past decade, most of the real gains in energy efficiency were developed for chips inside mobile electronics because of the demand for longer battery life. Dark silicon now represents the majority of mobile devices, multiple power islands are commonplace to push many functions into deep sleep, and performance is usually the secondary concern for most applications. Whil... » read more

Getting Formal With Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling Formal methodologies have always been an important tool in the verification engineer’s toolbox because they often can pinpoint bugs faster and with more accuracy than other verification approaches. The problem is that most engineers don’t know how to use them, and understanding this technology to a proficiency level requires a learning curve that most engineers consider pain... » read more

Lint Your Hardware Description: The Need To Be Fast, Accurate, Scalable And Flexible
By Various Writers - 14 Jun, 2012 - Comments: 0

A reliable linting tool must be SAFE (Scalable, Accurate, Fast and Extendible) so it can help catch issues early in the design cycle - issues that may be missed by traditional dynamic verification techniques. The main objective of a SAFE linting solution is to reduce costly design iterations, prevent late stage design ECOs and promote seamless reuse of IPs. Such a linting solution will need to ... » read more

New Reliability Issues
By Arvind Vel - 14 Jun, 2012 - Comments: 0

By Arvind Shanmugavel Reliability of ICs is a topic of growing concern with every technology node migration. With the onset of the 20nm process node from different foundries, reliability verification has taken center stage in design kits—and for good reason. Reliability margins have continued to decrease and have reached an inflection point at the 20nm node. The design and EDA communities ha... » read more

Power And Signal Line Electromigration Design And Reliability Validation Challenges
By Various Writers - 14 Jun, 2012 - Comments: 0

This white paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM-induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes. To download this paper, click here. » read more

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