November 2013 - Page 5 of 10 - Semiconductor Engineering

The Next Dimension
By Ed Sperling - 14 Nov, 2013 - Comments: 0

It’s hard to say definitively whether this is a trend or an aberration, but after what appears to have been a slam-dunk sprint to the finish line with finFETs some companies are re-evaluating their alternatives based upon return on investment. In place of perpetually shrinking features—and looming multipatterning at the next node—there is renewed interest in staying at 28nm with FDSOI,... » read more

IP Ecosystem Solutions For Complex Systems
By Joanne Itow - 14 Nov, 2013 - Comments: 0

At the Semico Impact Conference: Focus on the IP Ecosystem, Mahesh Tirupattur, Executive Vice President, Analog Bits, challenged four panelists to an engaging discussion on their approach to IP Ecosystem Solutions for Complex Systems. Panel participants included Dan Kochpatcharin, Deputy Director, IP Portfolio Management, TSMC; Jason Polychronopoulos, Mentor Graphics; Chris Rowen, Cadence Fello... » read more

3D-IC Standardization Progress Continues
By James Amano - 14 Nov, 2013 - Comments: 1

Since its formation in December 2010, the SEMI 3DS-IC Standards Committee has made significant progress in establishing key standards in areas such as TSV metrology, glass carrier wafers, and terminology. The committee’s two newest standards are SEMI 3D6-0913 - Guide for Chemical Mechanical Planarization (CMP) and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration, and S... » read more

From DFM To IFM
By Ed Sperling - 14 Nov, 2013 - Comments: 0

For the past decade the bridge between design and manufacturing was called, appropriately enough, design for manufacturing. DFM tools, which by nature cross boundaries of what previously were discrete segments in the semiconductor flow, are now critical for complex designs. They allow design teams to check early in the design process whether chips will yield sufficiently and to incorporate rule... » read more

Leti Outlines FDSOI And Monolithic 3D IC Roadmaps
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

Semiconductor Engineering discussed the future roadmaps for fully depleted silicon-on-insulator (FDSOI) technology and monolithic 3D chips with Maud Vinet, manager for the Innovative Devices Laboratory at CEA-Leti. SE: What are some of the technologies being developed at the Innovative Devices Laboratory? Vinet: The Innovative Devices Laboratory is involved with advanced CMOS. So basically... » read more

Collaborate Or Go Home
By Jeff Chappell - 14 Nov, 2013 - Comments: 0

Technology is hard. It's no secret that it's more difficult than ever to keep devices shrinking while increasing performance. It's also old news that it is increasingly costly to be at the leading edge, as semiconductor production technology gets ever more complex — even as a maturing chip industry becomes ever more dependent on low-cost consumer devices. But it has made for some strang... » read more

The Trouble With Triples—Part 1
By David Abercrombie - 14 Nov, 2013 - Comments: 0

If you’re a true geek like me, you may remember the Star Trek episode “The Trouble with Tribbles,” about the cute furry little aliens that purr when you pet them. They seemed so nice and friendly on the surface, but in the end, they became an exponentially growing mass of ravenous monsters that almost broke down the ship and consumed the storehouse of grain that was meant to provide human... » read more

More 3D Printing Applications
By Michael Watts - 14 Nov, 2013 - Comments: 0

There is enough news about 3D printing that the Guardian newspaper’s Web site even has a special section on it. The list of demonstrated applications runs the gamut from guns to panties via custom bobble head dolls and organs. It's interesting to look at all these ideas and try and work out which really has potential. There are 3 categories for potential: Practical. Possible with inv... » read more

Crunch Time
By Brian Fuller - 14 Nov, 2013 - Comments: 0

The electronics industry finds itself today at a tipping point (well, okay, another tipping point). Consider:  The network as we’ve known it for a couple of generations is changing before our eyes, not the least of which to accommodate the expected explosion of Internet of Things in the coming years. ARM CEO Simon Segars put it this way at the recent ARM TechCon event in Santa Clara: ... » read more

Tunnel FETs Emerge In Scaling Race
By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

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