November 2016 - Page 3 of 11 - Semiconductor Engineering


Verification Specialists And Generalists


Step into any weekly status update meeting where the topic is chip design verification, especially if formal verification is on the agenda, and it’s clear the verification department is moving much like traditional corporate environments. That is, there are generalists with loads of knowledge about many different verification tools and techniques and then there are specialists or experts who ... » read more

Avoiding The Barriers For Multi-Board Systems Design Development


Designing electronic systems that comprise multiple interacting boards, connectors and cables requires a multi-discipline team collaboration to effectively manage design complexity for optimum product performance and reliability. Multi-board systems may comprise two boards or up to hundreds of boards, packing a cabinet or rack, with interconnected connectors and/or cables. Since the hardware fu... » read more

What “Hamilton – An American Musical” Tickets And Emulation Have In Common


During a recent trip to New York, I managed to see “Hamilton, An American Musical”—despite the running joke about how hard it is to get tickets. The sale of “Hamilton” tickets teaches an interesting lesson about what I would call an “automatic feedback loop of value adjustment”. And believe it or not, it bears some resemblance to how verification users actually choose what engine ... » read more

Homogeneous And Heterogeneous Computing Collide


Eleven years ago processors stopped scaling due to diminishing returns and the breakdown of [getkc id="213" kc_name="Dennard's Law"]. That set in motion a chain of events from which the industry has still not fully recovered. The transition to homogeneous multi-core processing presented the software side with a problem that they did not know how to solve, namely how to optimize the usage of ... » read more

The Limits Of Parallelism


Parallelism used to be the domain of supercomputers working on weather simulations or plutonium decay. It is now part of the architecture of most SoCs. But just how efficient, effective and widespread has parallelism really become? There is no simple answer to that question. Even for a dual-core implementation of a processor on a chip, results can vary greatly by software application, operat... » read more

An Easier Path To Faster C With FPGAs


For most scientists, what is inside a high-performance computing platform is a mystery. All they usually want to know is that a platform will run an advanced algorithm thrown at it. What happens when a subject matter expert creates a powerful model for an algorithm that in turn automatically generates C code that runs too slowly? FPGA experts have created an answer. More and more, the genera... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

Constructing The Pillars Of The ARM HPC Ecosystem


In talking with HPC users at SC15 following the announcement of the OpenHPC project, I consistently heard that while they valued having a common open source framework covering a baseline set of HPC codes, they wanted to see more than one chip architecture represented. This is important when you consider that many HPC users are focused on getting to exascale computing for future supercomputer de... » read more

New Wave Of Consolidation


Consolidation is picking up again across the semiconductor industry, against a backdrop of looming interest rate hikes, geopolitical uncertainty, and the erosion of longstanding demarcations between markets. In the past couple of weeks, Siemens signed a deal to buy [getentity id="22017" e_name="Mentor Graphics"] for $4 billion, and [getentity id="22865" e_name="Samsung"] purchased Harman, a ... » read more

Can We Measure Next-Gen FinFETs?


After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

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