3D-IC Standards Key to TSV Adoption

By James Amano, director, SEMI International Standards

Three-Dimensional Stacked Integrated Circuits (3D-ICs) are composed of a stack of two-dimensional die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration methods like wirebond and flip chip have been in production for some time, but the next generation of 3D integration incorporates through-silicon via (TSV) technology as the primary method of interconnect between the die. While TSVs are one of the most rapidly developing technologies in the semiconductor industry, cost-effective high-volume manufacturing will be difficult to achieve unless manufacturing standards are developed. To help address this issue, on December 7, SEMI announced that it has formed a Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee.

3D-ICs promise a fundamental shift for current multi-chip integration and packaging approaches. 3D-ICs are already in production for CMOS image sensors; high-volume manufacturing for Wide Input/Output Synchronous Dynamic Random Access Memory (IO SDRAM) is expected in 2013. Widespread use of 3D-ICs would result in increased performance, smaller footprints, and reduced cost and power consumption. However, multiple manufacturing challenges must first be solved because 3D-ICs’ increased design and mechanical complexity can lead to signal interference, increased manufacturing defects, and thermal management issues.

To gather industry input and identify potential standardization topics, SEMI worked with SEMATECH to report recent progress, identify areas of concern for 3D TSV integration, and identify the gaps between existing technologies and future solutions. SEMATECH represents companies including GLOBALFOUNDRIES, HP, IBM, Intel, Samsung, and UMC. Other companies supporting the formation of a SEMI 3DS-IC Standards Committee include: Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron, and Xilinx.

Charter and Task Forces

The proposed charter for the 3DS-IC Committee is to explore, evaluate, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will:

• Promote mutual understanding and improved communication between users and suppliers of 3DS-IC materials, carriers, equipment, automation systems and devices
• Enhance the manufacturing efficiency, capability and shorten 3DS-IC time-to-market
• Reduce manufacturing cost in the 3DS-IC industry

The 3DS-IC Standards Committee will initially consist of three Task Forces:

• Bonded Wafer Pair (BWP) Task Force: This group will create a standard for BWP, using SEMI M1 (Specifications for Polished Single Crystal Silicon Wafers) as a starting point. The focus will be on TSV-focus, wafer-pair geometry, edges, and equipment issues with BWP. Andy Rudack (SEMATECH) is the Task Force leader.
• Inspection and Metrology Task Force: With no existing standards in place, the group will seek to identify and create new standards that address deficiencies for metrology and inspection created by 3DS-IC. This includes issues like TSV depth, BWP thickness/TTV, Microbump co-planarity, Defect, and Overlay. Chris Moore (Semilab) is the Task Force leader.
• Thin Wafer Carrier Task Force: Currently no standards exist so this group will identify and create new standards for thinned wafer carriers to address deficiencies created by 3DS-IC. Scope could include issues like thin wafer handling, thin wafer carriers (automation, shipping, process). Urmi Ray (Qualcomm) is the Task Force Leader.

First Face-to-Face Meeting in March

Initial face-to-face meetings of the SEMI 3DS-IC Standards Committee will occur at the SEMI Americas Spring Standards meetings in San Jose, California in March 2011. For information on SEMI Standards or on how to join the 3DS-IC Standards Committee, please contact James Amano at [email protected].