Significant technical advances are required to successfully manufacture vertical NAND designs.
One of the biggest developments taking place in the semiconductor industry is the emergence of 3D NAND memory technology. Products are available today that feature 3D NAND devices. It has taken years to become a reality — since Toshiba first discussed the concept of 3D NAND at the VLSI Symposium in 2007 – and now it is poised to replace planar NAND flash memory for storage.
The path that has led to this point is similar to what happened with the logic roadmap; despite innovative workarounds, the era of traditional planar “shrinks” for NAND is running out of steam. And, just as with logic, it has required significant technical advances to overcome the formidable challenges to successfully manufacture complex vertical 3D NAND designs.
Consolidating the transition to 3D NAND however raises key issues and will be the subject of an Applied Materials technical symposium, “3D NAND Is a Reality – What’s Next?” that I will be moderating on December 10th in Washington D.C. The list of panelists represent several industry leaders who can provide insights into where the industry is headed.
3D NAND is clearly a viable game-changer with leading-edge memory chipmakers investing major resources on this segment. The resulting reliability, density, performance, and lower power benefits will continue to drive this transition to vertical NAND. But while 3D NAND eases key planar scaling limitations, the question that arises is how far can vertical NAND itself be scaled? What issues will affect its scaling? Will 3D NAND continue lowering the cost per bit? What technologies will follow?
These and other questions will be discussed by technologists from SanDisk, Micron, SK Hynix, Macronix and Applied Materials. I hope you will plan to attend what promises to be an insightful discussion. Here is the link to register.
List below specific questions we should consider addressing during the panel discussion.
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