A Node By Any Other Name

Have you ever wondered what gives a particular CMOS technology node its name? When we talk about 20nm, 16nm or 14nm, what exactly does that number in front of the “nm” mean anyway? Is it the first layer metal half-pitch or the gate length (and while we’re at it, is that the printed gate length, the physical gate length, or the effective gate length)?

The half-pitch refers to half the minimum center-to-center distance spacing (or pitch) between Metal 1 lines. Mentor Graphics’ CEO, Wally Rhines, recently gave a keynote address titled “The Big Squeeze” at Mentor’s San Jose U2U event (archived here). He presented a nice slide that broke out the definitions for the various “gate lengths” commonly referred to in the industry and I’ve included it here in Figure 1.

Figure 1. Gate Length Definitions

If we go back to the early 1990s, all was well in semiconductor technology nodeland.  The metal half-pitch and the “gate length” were all in agreement, and a 0.5μm or 0.35μm process meant that those dimensions all lined up. Typically, the microprocessor process development teams were pushing for faster clocks to get more performance and so were trying to aggressively shrink gate lengths while memory (DRAM) process development teams were trying to reduce half-pitch in order to cram more bits onto a chip. This in part led to a divergence.

Heading into the late 1990s it started getting strange. Bill Arnold’s article [1] in Spectrum back in 2009 included a table listing the “node,” half-pitch and physical gate length for different “nodes.” He mentions that by the time we got to Intel’s “65nm” process in 2005 the gate length (actually he says width, but I’m pretty sure that he meant to say length) was 32nm and the half-pitch of the Metal 1 lines was 105nm. Clearly, the original “node” definition had been tossed to the side.

Bill mentions in his article that ITRS had actually abandoned the term in 2005, but some type of peace was negotiated and Wally even had a slide quoting the ITRS 2009 report as saying, “In the 2009 ITRS, we will discontinue the practice of eliminating references to the term `technology node.’”  Did you get that? Yeah, I had to read it twice. It’s a double negative.  Ironically in the year that Bill wrote his article, the ITRS brought the term “node” back (or at least discontinued the practice of eliminating it). In a previous blog on Thermals and New Technology Nodes, I wrote about TSMC and GlobalFoundries using their 20nm interconnect for their first generation 16/14nm FinFETs and that Intel was mentioned here in SemiWiki as having done the same from 32nm to 22n. Bringing back the term doesn’t seem to imply that things somehow magically started lining up again.

So the term “node” is still in use but what does it really mean? Well, this brings us to the latest ITRS report. In it there’s a detailed Overall Roadmap Technology Characteristics (ORTC) table available here and a summary report and table available here. Along the lines of you can’t tell the players apart without a program, I’ve included a summarized version of the summary table in Table1 along with an additional line for the FinFET fin width from the detailed ORTC Table (since there appears to be a discrepancy).

** Note: from the PIDS working group data; however, the calibration of Vdd, GLph, and I/CV is ongoing for improved targets in 2014 ITRS work.

Table 1: ITRS 2013 Data for CMOS Technology “Nodes”

Clearly the use of “fins” has created yet another spacing dimension to track. After all, FinFETs are made “wider” by adding more fins so the spacing of fins clearly plays into the area scaling for that technology. At the end of the day, designers are still looking at PPA (Power, Performance & Area). There’s still the expectation that each node will bring an improvement in those three areas although not necessarily to the same extent as was seen back in the days when a node was a node.
 
[1] B. Arnold, Shrinking Possibilities, IEEE Spectrum, April 1, 2009.