A Secret Weapon

By John Bainbridge
One of the major advances in SoC design methodologies more than a decade ago was the decoupling of the network-on-chip (NoC) from the individual IP cores throughout the SoC. This was (and is) accomplished through the use of carefully specified sockets such as OCP, the old VSIA VCI and (somewhat later) AMBA-AXI, which establish clear boundaries of communication responsibility and thereby enable independent development of IP cores.

The decoupling methodology, enabled by the network agents that isolate the cores from the network fabric, allows for the optimum provision of the local operating environment for each functional core to best meet that core’s basic communication needs (e.g. timing, protocol, data widths and addressing). It was a significant step in the introduction of Sonics’ NoC products.

These NoC products not only provide signal and protocol decoupling, which are now common to many NoC approaches, but also deliver performance layer decoupling. Performance decoupling enables better isolation of traffic flows through the network, with sophisticated quality-of-service management through the use of virtual channels (threads) and strategically positioned buffering within the network.

Sonics’ CTO, Drew Wingard, wrote a chapter in the book “Interconnect-Centric Design for Advanced NoCs and SoCs” about the various forms of decoupling that we believe are essential elements of advanced SoC platform design methodologies. When combined, these decoupling approaches enable rapid integration of arbitrary collections of IP cores and subsystems with high confidence in the correctness, functionality and performance of the resulting communication architecture.

Decoupling also enables us to introduce entirely new generations of NoC fabrics that can immediately leverage all of our customers’ existing IP assets.

Previous Sonics’ blogs have covered the value of decoupling as it relates to concurrent data flow, but now let’s look at a new, significant aspect of decoupling that is becoming increasingly vital to SoC designers—decoupling of power and clocking domains. As the former CTO of Silistix, a company that was founded on the concept of clock decoupling for NoCs, I am excited to see this technology truly come of age and mature right as customers are demanding more novel methodologies for sophisticated power management in next-generation SoC designs.

As SoC designers strive for lower power consumption, the number of clock and power domains continues to increase. These domains enable power reduction by switching off local supplies to eliminate leakage current, dynamically scaling voltages and clocks (especially in processing subsystems such as CPUs, GPUs and video engines) to optimize active power for operating conditions and altering IP core clocks to meet the needs of application usage scenarios. This increase in domains is also a function of the increase in the number of heterogeneous cores that are present in the SoC, which drives the need to provide Globally Asynchronous Locally Synchronous (GALS) networks that speed timing closure.

A properly architected network-on-chip needs to be able to deal natively with each of these domains, meaning flexible domain crossing choices, zero performance loss at a crossing, and importantly, allowing power-boundaries to be positioned anywhere within the network. Having the ability to partition the SoC into many fine-grained, separately controlled domains, enables the SoC designer to tune each IP core or subsystem to minimize energy consumption. That enables new levels of power control. Aggressive power management is, without a doubt, a key differentiator in this mobile device-crazed market.

So having the ability to effectively decouple the system has become critical to many aspects of advanced SoC development, including having a much more robust design methodology and superior system performance by allowing more data flow concurrency—and now, superior power management. On the surface, decoupling may sound like an esoteric concept, but ultimately may be a secret weapon for SoC design..

–John Bainbridge is a technologist in the office of the CTO at Sonics.