AL2012 – A Prologue

Will there be any surprises in lithography this year?

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Yesterday I found my way to San Jose (a more arduous journey than in the past, since all direct flights from Austin to San Jose have disappeared like civility in American politics).  Another SPIE Advanced Lithography Conference is about to begin.  As usual, I will blog each day from my vantage as an overwhelmed conference participant.  And also as usual, I will set the stage for what I think will be the highlights of the week in this prologue.  I hope, of course, that I am wrong – that will mean that I don’t know what will be important and a surprise is in store.  Surprises are the best thing about this conference.  And I have never been bored here yet.

Let’s begin with the obvious topic:  EUV lithography.  I believe that 2012 will be the make or break year for EUVL.  I’ve said that before.  In 2010 and 2011, in fact.  I continue to be amazed at how willing customers are to live with missed specs and slipped deadlines.  I guess that’s what happens when you have no alternatives.  But this time I mean it:  2012 is the make or break year for EUV.  And of course, all eyes are on ASML and their source suppliers.

Last year ASML shipped 6 NXE:3100 “pre-production” EUV tools (actually, the first one was in 2010), at an estimated $120M each.  While spec’ed at 60 wafers per hour throughput, they delivered 6 wph.  An upgrade of the source by Cymer to bring that close to 20 wph has been delayed.  Meanwhile, the production tool NXE:3300 is supposedly still on schedule for delivery in the second half of this year.  But wait:  the spec on throughput for the 3300 has changed.  It is now 69 wph, down from an original 125 wph, which is down from even higher expectations.  The higher 125 number will come later, we are told, with an upgrade to the source.  It’s all about managing expectations.  And twisting arms.  Did I mention there are no alternatives?

But expectations are not the only thing that matters.  Eventually, real throughput on real product will matter.  Which brings up an interesting question – one that I hope to gain more insight on this week.  How high does “high” have to be in High Volume Manufacturing (HVM)?  What’s the lowest actual production throughput that customers can live with and still think EUV was worth the commitment?  The fabs aren’t talking.  Understandably, they don’t want to give ASML the lowest number, since that will take the pressure off them to do better.  And different customers will have very different answers, I’m sure.  Will Intel buy 10 EUV tools if those tools can only deliver 40 wph in production?

A related but more technical question is also on my mind:  How much line-edge roughness (LER) can devices tolerate at the 14-nm node and below?  This question is related to throughput because the easy way (and maybe the only way) to reduce LER is to increase exposure dose.  And in source-limited technologies like EUV and electron-beam lithography, throughput is mostly determined by the resist dose requirement.  (See my previous posts on Tennant’s Law.)  So, as always, I’ll be focusing on the LER papers this week, hoping to gain enough insight to say I actually understand LER, what causes it, and how small it can be made.

As I’ve said before, LER is the ultimate limiter of resolution.  Unless, that is, we break the LER paradigm of our current exposure and resist approaches.  One way to do that is with directed self-assembly (DSA).  This year’s hot topic will, no doubt, be DSA.  The technology has shown enough promise that it has gotten the industry excited, and there has been a lot of activity in the last year.  Soon, however, and maybe this week, reality will set in.  Getting DSA to work in production will take an enormous effort.

I’ve seen these cycles before:  A promising new idea gets people excited.  There is potential to solve a nagging industry problem, or enable a future generation of products.  After the early adopters report on their progress (and those reports are always glowing), the early followers jump in and start working out the details.  Then they come to this conference and start reporting on the problems they are having.  Solutions to those problems are proposed and people get back to work.  But do the solutions come fast enough, or does the excitement wane?  If the problems pile up too fast, people looking for a quick fix give up.  A few diehards labor on.  Progress is slow, coupled with complaints that EUV is getting all the resources.  Will the new idea survive these travails, eventually become a “plan of record” at enough fabs to be self-supporting?  The answer will depend on the difficulty of the problem and the grit and wits of the diehards.

Does this sound familiar?  It could describe sidewall-spacer double patterning (made it), or litho-freeze-litho-freeze double patterning (hasn’t made it), or model-based OPC (made it), or imprint (hasn’t made it).  And it will describe DSA, though we are a few years away from knowing the outcome.

What else will I be watching for this week?  Ah yes, the surprises.  Hopefully, I won’t be in the wrong session when they occur.


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